mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 20:24:29 +07:00
839d9bda2f
Run the micro-USB A/B port on Jetson TK1 in host mode by default. Signed-off-by: Thierry Reding <treding@nvidia.com>
2078 lines
56 KiB
Plaintext
2078 lines
56 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
/dts-v1/;
|
|
|
|
#include <dt-bindings/input/input.h>
|
|
#include "tegra124.dtsi"
|
|
|
|
#include "tegra124-jetson-tk1-emc.dtsi"
|
|
|
|
/ {
|
|
model = "NVIDIA Tegra124 Jetson TK1";
|
|
compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
|
|
|
|
aliases {
|
|
rtc0 = "/i2c@7000d000/pmic@40";
|
|
rtc1 = "/rtc@7000e000";
|
|
|
|
/* This order keeps the mapping DB9 connector <-> ttyS0 */
|
|
serial0 = &uartd;
|
|
serial1 = &uarta;
|
|
serial2 = &uartb;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
memory@80000000 {
|
|
reg = <0x0 0x80000000 0x0 0x80000000>;
|
|
};
|
|
|
|
pcie@1003000 {
|
|
status = "okay";
|
|
|
|
avddio-pex-supply = <&vdd_1v05_run>;
|
|
dvddio-pex-supply = <&vdd_1v05_run>;
|
|
avdd-pex-pll-supply = <&vdd_1v05_run>;
|
|
hvdd-pex-supply = <&vdd_3v3_lp0>;
|
|
hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
|
|
vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
|
|
avdd-pll-erefe-supply = <&avdd_1v05_run>;
|
|
|
|
/* Mini PCIe */
|
|
pci@1,0 {
|
|
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
|
|
phy-names = "pcie-0";
|
|
status = "okay";
|
|
};
|
|
|
|
/* Gigabit Ethernet */
|
|
pci@2,0 {
|
|
phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
|
|
phy-names = "pcie-0";
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
host1x@50000000 {
|
|
hdmi@54280000 {
|
|
status = "okay";
|
|
|
|
hdmi-supply = <&vdd_5v0_hdmi>;
|
|
pll-supply = <&vdd_hdmi_pll>;
|
|
vdd-supply = <&vdd_3v3_hdmi>;
|
|
|
|
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
|
|
nvidia,hpd-gpio =
|
|
<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
|
|
};
|
|
};
|
|
|
|
cec@70015000 {
|
|
status = "okay";
|
|
};
|
|
|
|
gpu@0,57000000 {
|
|
/*
|
|
* Node left disabled on purpose - the bootloader will enable
|
|
* it after having set the VPR up
|
|
*/
|
|
vdd-supply = <&vdd_gpu>;
|
|
};
|
|
|
|
pinmux: pinmux@70000868 {
|
|
pinctrl-names = "boot";
|
|
pinctrl-0 = <&state_boot>;
|
|
|
|
state_boot: pinmux {
|
|
clk_32k_out_pa0 {
|
|
nvidia,pins = "clk_32k_out_pa0";
|
|
nvidia,function = "soc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
uart3_cts_n_pa1 {
|
|
nvidia,pins = "uart3_cts_n_pa1";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap2_fs_pa2 {
|
|
nvidia,pins = "dap2_fs_pa2";
|
|
nvidia,function = "i2s1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap2_sclk_pa3 {
|
|
nvidia,pins = "dap2_sclk_pa3";
|
|
nvidia,function = "i2s1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap2_din_pa4 {
|
|
nvidia,pins = "dap2_din_pa4";
|
|
nvidia,function = "i2s1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
dap2_dout_pa5 {
|
|
nvidia,pins = "dap2_dout_pa5";
|
|
nvidia,function = "i2s1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc3_clk_pa6 {
|
|
nvidia,pins = "sdmmc3_clk_pa6";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3_cmd_pa7 {
|
|
nvidia,pins = "sdmmc3_cmd_pa7";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pb0 {
|
|
nvidia,pins = "pb0";
|
|
nvidia,function = "uartd";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pb1 {
|
|
nvidia,pins = "pb1";
|
|
nvidia,function = "uartd";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3_dat3_pb4 {
|
|
nvidia,pins = "sdmmc3_dat3_pb4";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3_dat2_pb5 {
|
|
nvidia,pins = "sdmmc3_dat2_pb5";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3_dat1_pb6 {
|
|
nvidia,pins = "sdmmc3_dat1_pb6";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3_dat0_pb7 {
|
|
nvidia,pins = "sdmmc3_dat0_pb7";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
uart3_rts_n_pc0 {
|
|
nvidia,pins = "uart3_rts_n_pc0";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart2_txd_pc2 {
|
|
nvidia,pins = "uart2_txd_pc2";
|
|
nvidia,function = "irda";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart2_rxd_pc3 {
|
|
nvidia,pins = "uart2_rxd_pc3";
|
|
nvidia,function = "irda";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gen1_i2c_scl_pc4 {
|
|
nvidia,pins = "gen1_i2c_scl_pc4";
|
|
nvidia,function = "i2c1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gen1_i2c_sda_pc5 {
|
|
nvidia,pins = "gen1_i2c_sda_pc5";
|
|
nvidia,function = "i2c1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pc7 {
|
|
nvidia,pins = "pc7";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pg0 {
|
|
nvidia,pins = "pg0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pg1 {
|
|
nvidia,pins = "pg1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pg2 {
|
|
nvidia,pins = "pg2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pg3 {
|
|
nvidia,pins = "pg3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pg4 {
|
|
nvidia,pins = "pg4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pg5 {
|
|
nvidia,pins = "pg5";
|
|
nvidia,function = "spi4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pg6 {
|
|
nvidia,pins = "pg6";
|
|
nvidia,function = "spi4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pg7 {
|
|
nvidia,pins = "pg7";
|
|
nvidia,function = "spi4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
ph0 {
|
|
nvidia,pins = "ph0";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ph1 {
|
|
nvidia,pins = "ph1";
|
|
nvidia,function = "pwm1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ph2 {
|
|
nvidia,pins = "ph2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ph3 {
|
|
nvidia,pins = "ph3";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ph4 {
|
|
nvidia,pins = "ph4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
ph5 {
|
|
nvidia,pins = "ph5";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ph6 {
|
|
nvidia,pins = "ph6";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ph7 {
|
|
nvidia,pins = "ph7";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pi0 {
|
|
nvidia,pins = "pi0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pi1 {
|
|
nvidia,pins = "pi1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pi2 {
|
|
nvidia,pins = "pi2";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pi3 {
|
|
nvidia,pins = "pi3";
|
|
nvidia,function = "spi4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pi4 {
|
|
nvidia,pins = "pi4";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pi5 {
|
|
nvidia,pins = "pi5";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pi6 {
|
|
nvidia,pins = "pi6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pi7 {
|
|
nvidia,pins = "pi7";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pj0 {
|
|
nvidia,pins = "pj0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pj2 {
|
|
nvidia,pins = "pj2";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart2_cts_n_pj5 {
|
|
nvidia,pins = "uart2_cts_n_pj5";
|
|
nvidia,function = "uartb";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
uart2_rts_n_pj6 {
|
|
nvidia,pins = "uart2_rts_n_pj6";
|
|
nvidia,function = "uartb";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pj7 {
|
|
nvidia,pins = "pj7";
|
|
nvidia,function = "uartd";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk0 {
|
|
nvidia,pins = "pk0";
|
|
nvidia,function = "rsvd1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk1 {
|
|
nvidia,pins = "pk1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk2 {
|
|
nvidia,pins = "pk2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pk3 {
|
|
nvidia,pins = "pk3";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk4 {
|
|
nvidia,pins = "pk4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
spdif_out_pk5 {
|
|
nvidia,pins = "spdif_out_pk5";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
spdif_in_pk6 {
|
|
nvidia,pins = "spdif_in_pk6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pk7 {
|
|
nvidia,pins = "pk7";
|
|
nvidia,function = "uartd";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap1_fs_pn0 {
|
|
nvidia,pins = "dap1_fs_pn0";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap1_din_pn1 {
|
|
nvidia,pins = "dap1_din_pn1";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap1_dout_pn2 {
|
|
nvidia,pins = "dap1_dout_pn2";
|
|
nvidia,function = "sata";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap1_sclk_pn3 {
|
|
nvidia,pins = "dap1_sclk_pn3";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
usb_vbus_en0_pn4 {
|
|
nvidia,pins = "usb_vbus_en0_pn4";
|
|
nvidia,function = "usb";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
usb_vbus_en1_pn5 {
|
|
nvidia,pins = "usb_vbus_en1_pn5";
|
|
nvidia,function = "usb";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
hdmi_int_pn7 {
|
|
nvidia,pins = "hdmi_int_pn7";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_data7_po0 {
|
|
nvidia,pins = "ulpi_data7_po0";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_data0_po1 {
|
|
nvidia,pins = "ulpi_data0_po1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
ulpi_data1_po2 {
|
|
nvidia,pins = "ulpi_data1_po2";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_data2_po3 {
|
|
nvidia,pins = "ulpi_data2_po3";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_data3_po4 {
|
|
nvidia,pins = "ulpi_data3_po4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
ulpi_data4_po5 {
|
|
nvidia,pins = "ulpi_data4_po5";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_data5_po6 {
|
|
nvidia,pins = "ulpi_data5_po6";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_data6_po7 {
|
|
nvidia,pins = "ulpi_data6_po7";
|
|
nvidia,function = "ulpi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap3_fs_pp0 {
|
|
nvidia,pins = "dap3_fs_pp0";
|
|
nvidia,function = "i2s2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap3_din_pp1 {
|
|
nvidia,pins = "dap3_din_pp1";
|
|
nvidia,function = "i2s2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap3_dout_pp2 {
|
|
nvidia,pins = "dap3_dout_pp2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap3_sclk_pp3 {
|
|
nvidia,pins = "dap3_sclk_pp3";
|
|
nvidia,function = "rsvd3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap4_fs_pp4 {
|
|
nvidia,pins = "dap4_fs_pp4";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap4_din_pp5 {
|
|
nvidia,pins = "dap4_din_pp5";
|
|
nvidia,function = "rsvd3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap4_dout_pp6 {
|
|
nvidia,pins = "dap4_dout_pp6";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap4_sclk_pp7 {
|
|
nvidia,pins = "dap4_sclk_pp7";
|
|
nvidia,function = "rsvd3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_col0_pq0 {
|
|
nvidia,pins = "kb_col0_pq0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
kb_col1_pq1 {
|
|
nvidia,pins = "kb_col1_pq1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_col2_pq2 {
|
|
nvidia,pins = "kb_col2_pq2";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_col3_pq3 {
|
|
nvidia,pins = "kb_col3_pq3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
kb_col4_pq4 {
|
|
nvidia,pins = "kb_col4_pq4";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
kb_col5_pq5 {
|
|
nvidia,pins = "kb_col5_pq5";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
kb_col6_pq6 {
|
|
nvidia,pins = "kb_col6_pq6";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_col7_pq7 {
|
|
nvidia,pins = "kb_col7_pq7";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row0_pr0 {
|
|
nvidia,pins = "kb_row0_pr0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row1_pr1 {
|
|
nvidia,pins = "kb_row1_pr1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row2_pr2 {
|
|
nvidia,pins = "kb_row2_pr2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row3_pr3 {
|
|
nvidia,pins = "kb_row3_pr3";
|
|
nvidia,function = "kbc";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row4_pr4 {
|
|
nvidia,pins = "kb_row4_pr4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
kb_row5_pr5 {
|
|
nvidia,pins = "kb_row5_pr5";
|
|
nvidia,function = "rsvd3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row6_pr6 {
|
|
nvidia,pins = "kb_row6_pr6";
|
|
nvidia,function = "displaya_alt";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
kb_row7_pr7 {
|
|
nvidia,pins = "kb_row7_pr7";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
kb_row8_ps0 {
|
|
nvidia,pins = "kb_row8_ps0";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row9_ps1 {
|
|
nvidia,pins = "kb_row9_ps1";
|
|
nvidia,function = "uarta";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row10_ps2 {
|
|
nvidia,pins = "kb_row10_ps2";
|
|
nvidia,function = "uarta";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
kb_row11_ps3 {
|
|
nvidia,pins = "kb_row11_ps3";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row12_ps4 {
|
|
nvidia,pins = "kb_row12_ps4";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row13_ps5 {
|
|
nvidia,pins = "kb_row13_ps5";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row14_ps6 {
|
|
nvidia,pins = "kb_row14_ps6";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row15_ps7 {
|
|
nvidia,pins = "kb_row15_ps7";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
kb_row16_pt0 {
|
|
nvidia,pins = "kb_row16_pt0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
kb_row17_pt1 {
|
|
nvidia,pins = "kb_row17_pt1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gen2_i2c_scl_pt5 {
|
|
nvidia,pins = "gen2_i2c_scl_pt5";
|
|
nvidia,function = "i2c2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gen2_i2c_sda_pt6 {
|
|
nvidia,pins = "gen2_i2c_sda_pt6";
|
|
nvidia,function = "i2c2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_cmd_pt7 {
|
|
nvidia,pins = "sdmmc4_cmd_pt7";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pu0 {
|
|
nvidia,pins = "pu0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pu1 {
|
|
nvidia,pins = "pu1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pu2 {
|
|
nvidia,pins = "pu2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pu3 {
|
|
nvidia,pins = "pu3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pu4 {
|
|
nvidia,pins = "pu4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pu5 {
|
|
nvidia,pins = "pu5";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pu6 {
|
|
nvidia,pins = "pu6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pv0 {
|
|
nvidia,pins = "pv0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pv1 {
|
|
nvidia,pins = "pv1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3_cd_n_pv2 {
|
|
nvidia,pins = "sdmmc3_cd_n_pv2";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc1_wp_n_pv3 {
|
|
nvidia,pins = "sdmmc1_wp_n_pv3";
|
|
nvidia,function = "sdmmc1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ddc_scl_pv4 {
|
|
nvidia,pins = "ddc_scl_pv4";
|
|
nvidia,function = "i2c4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ddc_sda_pv5 {
|
|
nvidia,pins = "ddc_sda_pv5";
|
|
nvidia,function = "i2c4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_w2_aud_pw2 {
|
|
nvidia,pins = "gpio_w2_aud_pw2";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_w3_aud_pw3 {
|
|
nvidia,pins = "gpio_w3_aud_pw3";
|
|
nvidia,function = "spi6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap_mclk1_pw4 {
|
|
nvidia,pins = "dap_mclk1_pw4";
|
|
nvidia,function = "extperiph1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
clk2_out_pw5 {
|
|
nvidia,pins = "clk2_out_pw5";
|
|
nvidia,function = "extperiph2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart3_txd_pw6 {
|
|
nvidia,pins = "uart3_txd_pw6";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
uart3_rxd_pw7 {
|
|
nvidia,pins = "uart3_rxd_pw7";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dvfs_pwm_px0 {
|
|
nvidia,pins = "dvfs_pwm_px0";
|
|
nvidia,function = "cldvfs";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_x1_aud_px1 {
|
|
nvidia,pins = "gpio_x1_aud_px1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
dvfs_clk_px2 {
|
|
nvidia,pins = "dvfs_clk_px2";
|
|
nvidia,function = "cldvfs";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_x3_aud_px3 {
|
|
nvidia,pins = "gpio_x3_aud_px3";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_x4_aud_px4 {
|
|
nvidia,pins = "gpio_x4_aud_px4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
gpio_x5_aud_px5 {
|
|
nvidia,pins = "gpio_x5_aud_px5";
|
|
nvidia,function = "rsvd4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_x6_aud_px6 {
|
|
nvidia,pins = "gpio_x6_aud_px6";
|
|
nvidia,function = "gmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
gpio_x7_aud_px7 {
|
|
nvidia,pins = "gpio_x7_aud_px7";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_clk_py0 {
|
|
nvidia,pins = "ulpi_clk_py0";
|
|
nvidia,function = "spi1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_dir_py1 {
|
|
nvidia,pins = "ulpi_dir_py1";
|
|
nvidia,function = "spi1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
ulpi_nxt_py2 {
|
|
nvidia,pins = "ulpi_nxt_py2";
|
|
nvidia,function = "spi1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
ulpi_stp_py3 {
|
|
nvidia,pins = "ulpi_stp_py3";
|
|
nvidia,function = "spi1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc1_dat3_py4 {
|
|
nvidia,pins = "sdmmc1_dat3_py4";
|
|
nvidia,function = "sdmmc1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc1_dat2_py5 {
|
|
nvidia,pins = "sdmmc1_dat2_py5";
|
|
nvidia,function = "sdmmc1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc1_dat1_py6 {
|
|
nvidia,pins = "sdmmc1_dat1_py6";
|
|
nvidia,function = "sdmmc1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc1_dat0_py7 {
|
|
nvidia,pins = "sdmmc1_dat0_py7";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc1_clk_pz0 {
|
|
nvidia,pins = "sdmmc1_clk_pz0";
|
|
nvidia,function = "rsvd3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc1_cmd_pz1 {
|
|
nvidia,pins = "sdmmc1_cmd_pz1";
|
|
nvidia,function = "sdmmc1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pwr_i2c_scl_pz6 {
|
|
nvidia,pins = "pwr_i2c_scl_pz6";
|
|
nvidia,function = "i2cpwr";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pwr_i2c_sda_pz7 {
|
|
nvidia,pins = "pwr_i2c_sda_pz7";
|
|
nvidia,function = "i2cpwr";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat0_paa0 {
|
|
nvidia,pins = "sdmmc4_dat0_paa0";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat1_paa1 {
|
|
nvidia,pins = "sdmmc4_dat1_paa1";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat2_paa2 {
|
|
nvidia,pins = "sdmmc4_dat2_paa2";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat3_paa3 {
|
|
nvidia,pins = "sdmmc4_dat3_paa3";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat4_paa4 {
|
|
nvidia,pins = "sdmmc4_dat4_paa4";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat5_paa5 {
|
|
nvidia,pins = "sdmmc4_dat5_paa5";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat6_paa6 {
|
|
nvidia,pins = "sdmmc4_dat6_paa6";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_dat7_paa7 {
|
|
nvidia,pins = "sdmmc4_dat7_paa7";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pbb0 {
|
|
nvidia,pins = "pbb0";
|
|
nvidia,function = "vimclk2_alt";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cam_i2c_scl_pbb1 {
|
|
nvidia,pins = "cam_i2c_scl_pbb1";
|
|
nvidia,function = "i2c3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
cam_i2c_sda_pbb2 {
|
|
nvidia,pins = "cam_i2c_sda_pbb2";
|
|
nvidia,function = "i2c3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pbb3 {
|
|
nvidia,pins = "pbb3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pbb4 {
|
|
nvidia,pins = "pbb4";
|
|
nvidia,function = "vgp4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pbb5 {
|
|
nvidia,pins = "pbb5";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pbb6 {
|
|
nvidia,pins = "pbb6";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pbb7 {
|
|
nvidia,pins = "pbb7";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cam_mclk_pcc0 {
|
|
nvidia,pins = "cam_mclk_pcc0";
|
|
nvidia,function = "vi_alt3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pcc1 {
|
|
nvidia,pins = "pcc1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pcc2 {
|
|
nvidia,pins = "pcc2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc4_clk_pcc4 {
|
|
nvidia,pins = "sdmmc4_clk_pcc4";
|
|
nvidia,function = "sdmmc4";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
clk2_req_pcc5 {
|
|
nvidia,pins = "clk2_req_pcc5";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pex_l0_rst_n_pdd1 {
|
|
nvidia,pins = "pex_l0_rst_n_pdd1";
|
|
nvidia,function = "pe0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pex_l0_clkreq_n_pdd2 {
|
|
nvidia,pins = "pex_l0_clkreq_n_pdd2";
|
|
nvidia,function = "pe0";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pex_wake_n_pdd3 {
|
|
nvidia,pins = "pex_wake_n_pdd3";
|
|
nvidia,function = "pe";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
pex_l1_rst_n_pdd5 {
|
|
nvidia,pins = "pex_l1_rst_n_pdd5";
|
|
nvidia,function = "pe1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pex_l1_clkreq_n_pdd6 {
|
|
nvidia,pins = "pex_l1_clkreq_n_pdd6";
|
|
nvidia,function = "pe1";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
clk3_out_pee0 {
|
|
nvidia,pins = "clk3_out_pee0";
|
|
nvidia,function = "extperiph3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
clk3_req_pee1 {
|
|
nvidia,pins = "clk3_req_pee1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dap_mclk1_req_pee2 {
|
|
nvidia,pins = "dap_mclk1_req_pee2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
hdmi_cec_pee3 {
|
|
nvidia,pins = "hdmi_cec_pee3";
|
|
nvidia,function = "cec";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
sdmmc3_clk_lb_out_pee4 {
|
|
nvidia,pins = "sdmmc3_clk_lb_out_pee4";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
sdmmc3_clk_lb_in_pee5 {
|
|
nvidia,pins = "sdmmc3_clk_lb_in_pee5";
|
|
nvidia,function = "sdmmc3";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
dp_hpd_pff0 {
|
|
nvidia,pins = "dp_hpd_pff0";
|
|
nvidia,function = "dp";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
usb_vbus_en2_pff1 {
|
|
nvidia,pins = "usb_vbus_en2_pff1";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pff2 {
|
|
nvidia,pins = "pff2";
|
|
nvidia,function = "rsvd2";
|
|
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
core_pwr_req {
|
|
nvidia,pins = "core_pwr_req";
|
|
nvidia,function = "pwron";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
cpu_pwr_req {
|
|
nvidia,pins = "cpu_pwr_req";
|
|
nvidia,function = "cpu";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
pwr_int_n {
|
|
nvidia,pins = "pwr_int_n";
|
|
nvidia,function = "pmi";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
reset_out_n {
|
|
nvidia,pins = "reset_out_n";
|
|
nvidia,function = "reset_out_n";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
clk_32k_in {
|
|
nvidia,pins = "clk_32k_in";
|
|
nvidia,function = "clk";
|
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
|
};
|
|
jtag_rtck {
|
|
nvidia,pins = "jtag_rtck";
|
|
nvidia,function = "rtck";
|
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
|
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
|
};
|
|
dsi_b {
|
|
nvidia,pins = "mipi_pad_ctrl_dsi_b";
|
|
nvidia,function = "dsi_b";
|
|
};
|
|
};
|
|
};
|
|
|
|
/*
|
|
* First high speed UART, exposed on the expansion connector J3A2
|
|
* Pin 41: BR_UART1_TXD
|
|
* Pin 44: BR_UART1_RXD
|
|
*/
|
|
serial@70006000 {
|
|
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
|
|
status = "okay";
|
|
};
|
|
|
|
/*
|
|
* Second high speed UART, exposed on the expansion connector J3A2
|
|
* Pin 65: UART2_RXD
|
|
* Pin 68: UART2_TXD
|
|
* Pin 71: UART2_CTS_L
|
|
* Pin 74: UART2_RTS_L
|
|
*/
|
|
serial@70006040 {
|
|
compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart";
|
|
status = "okay";
|
|
};
|
|
|
|
/* DB9 serial port */
|
|
serial@70006300 {
|
|
status = "okay";
|
|
};
|
|
|
|
/* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */
|
|
i2c@7000c000 {
|
|
status = "okay";
|
|
clock-frequency = <100000>;
|
|
|
|
rt5639: audio-codec@1c {
|
|
compatible = "realtek,rt5639";
|
|
reg = <0x1c>;
|
|
interrupt-parent = <&gpio>;
|
|
interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
|
|
realtek,ldo1-en-gpios =
|
|
<&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
temperature-sensor@4c {
|
|
compatible = "ti,tmp451";
|
|
reg = <0x4c>;
|
|
interrupt-parent = <&gpio>;
|
|
interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
eeprom@56 {
|
|
compatible = "atmel,24c02";
|
|
reg = <0x56>;
|
|
pagesize = <8>;
|
|
};
|
|
};
|
|
|
|
/* Expansion GEN2_I2C_* */
|
|
i2c@7000c400 {
|
|
status = "okay";
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
/* Expansion CAM_I2C_* */
|
|
i2c@7000c500 {
|
|
status = "okay";
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
/* HDMI DDC */
|
|
hdmi_ddc: i2c@7000c700 {
|
|
status = "okay";
|
|
clock-frequency = <100000>;
|
|
};
|
|
|
|
/* Expansion PWR_I2C_*, on-board components */
|
|
i2c@7000d000 {
|
|
status = "okay";
|
|
clock-frequency = <400000>;
|
|
|
|
pmic: pmic@40 {
|
|
compatible = "ams,as3722";
|
|
reg = <0x40>;
|
|
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
ams,system-power-controller;
|
|
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&as3722_default>;
|
|
|
|
as3722_default: pinmux {
|
|
gpio0 {
|
|
pins = "gpio0";
|
|
function = "gpio";
|
|
bias-pull-down;
|
|
};
|
|
|
|
gpio1_2_4_7 {
|
|
pins = "gpio1", "gpio2", "gpio4", "gpio7";
|
|
function = "gpio";
|
|
bias-pull-up;
|
|
};
|
|
|
|
gpio3_5_6 {
|
|
pins = "gpio3", "gpio5", "gpio6";
|
|
bias-high-impedance;
|
|
};
|
|
};
|
|
|
|
regulators {
|
|
vsup-sd2-supply = <&vdd_5v0_sys>;
|
|
vsup-sd3-supply = <&vdd_5v0_sys>;
|
|
vsup-sd4-supply = <&vdd_5v0_sys>;
|
|
vsup-sd5-supply = <&vdd_5v0_sys>;
|
|
vin-ldo0-supply = <&vdd_1v35_lp0>;
|
|
vin-ldo1-6-supply = <&vdd_3v3_run>;
|
|
vin-ldo2-5-7-supply = <&vddio_1v8>;
|
|
vin-ldo3-4-supply = <&vdd_3v3_sys>;
|
|
vin-ldo9-10-supply = <&vdd_5v0_sys>;
|
|
vin-ldo11-supply = <&vdd_3v3_run>;
|
|
|
|
vdd_cpu: sd0 {
|
|
regulator-name = "+VDD_CPU_AP";
|
|
regulator-min-microvolt = <700000>;
|
|
regulator-max-microvolt = <1400000>;
|
|
regulator-min-microamp = <3500000>;
|
|
regulator-max-microamp = <3500000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
ams,ext-control = <2>;
|
|
};
|
|
|
|
sd1 {
|
|
regulator-name = "+VDD_CORE";
|
|
regulator-min-microvolt = <700000>;
|
|
regulator-max-microvolt = <1350000>;
|
|
regulator-min-microamp = <2500000>;
|
|
regulator-max-microamp = <2500000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
ams,ext-control = <1>;
|
|
};
|
|
|
|
vdd_1v35_lp0: sd2 {
|
|
regulator-name = "+1.35V_LP0(sd2)";
|
|
regulator-min-microvolt = <1350000>;
|
|
regulator-max-microvolt = <1350000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
sd3 {
|
|
regulator-name = "+1.35V_LP0(sd3)";
|
|
regulator-min-microvolt = <1350000>;
|
|
regulator-max-microvolt = <1350000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
vdd_1v05_run: sd4 {
|
|
regulator-name = "+1.05V_RUN";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
};
|
|
|
|
vddio_1v8: sd5 {
|
|
regulator-name = "+1.8V_VDDIO";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vdd_gpu: sd6 {
|
|
regulator-name = "+VDD_GPU_AP";
|
|
regulator-min-microvolt = <650000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-min-microamp = <3500000>;
|
|
regulator-max-microamp = <3500000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
avdd_1v05_run: ldo0 {
|
|
regulator-name = "+1.05V_RUN_AVDD";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
ams,ext-control = <1>;
|
|
};
|
|
|
|
ldo1 {
|
|
regulator-name = "+1.8V_RUN_CAM";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
ldo2 {
|
|
regulator-name = "+1.2V_GEN_AVDD";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
ldo3 {
|
|
regulator-name = "+1.05V_LP0_VDD_RTC";
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <1000000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
ams,enable-tracking;
|
|
};
|
|
|
|
ldo4 {
|
|
regulator-name = "+2.8V_RUN_CAM";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
};
|
|
|
|
ldo5 {
|
|
regulator-name = "+1.2V_RUN_CAM_FRONT";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
};
|
|
|
|
vddio_sdmmc3: ldo6 {
|
|
regulator-name = "+VDDIO_SDMMC3";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
|
|
ldo7 {
|
|
regulator-name = "+1.05V_RUN_CAM_REAR";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
};
|
|
|
|
ldo9 {
|
|
regulator-name = "+3.3V_RUN_TOUCH";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
};
|
|
|
|
ldo10 {
|
|
regulator-name = "+2.8V_RUN_CAM_AF";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
};
|
|
|
|
ldo11 {
|
|
regulator-name = "+1.8V_RUN_VPP_FUSE";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
/* Expansion TS_SPI_* */
|
|
spi@7000d400 {
|
|
status = "okay";
|
|
};
|
|
|
|
/* Internal SPI */
|
|
spi@7000da00 {
|
|
status = "okay";
|
|
spi-max-frequency = <25000000>;
|
|
spi-flash@0 {
|
|
compatible = "winbond,w25q32dw", "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <20000000>;
|
|
};
|
|
};
|
|
|
|
pmc@7000e400 {
|
|
nvidia,invert-interrupt;
|
|
nvidia,suspend-mode = <1>;
|
|
nvidia,cpu-pwr-good-time = <500>;
|
|
nvidia,cpu-pwr-off-time = <300>;
|
|
nvidia,core-pwr-good-time = <641 3845>;
|
|
nvidia,core-pwr-off-time = <61036>;
|
|
nvidia,core-power-req-active-high;
|
|
nvidia,sys-clock-req-active-high;
|
|
|
|
i2c-thermtrip {
|
|
nvidia,i2c-controller-id = <4>;
|
|
nvidia,bus-addr = <0x40>;
|
|
nvidia,reg-addr = <0x36>;
|
|
nvidia,reg-data = <0x2>;
|
|
};
|
|
};
|
|
|
|
/* Serial ATA */
|
|
sata@70020000 {
|
|
status = "okay";
|
|
|
|
phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
|
|
phy-names = "sata-0";
|
|
|
|
hvdd-supply = <&vdd_3v3_lp0>;
|
|
vddio-supply = <&vdd_1v05_run>;
|
|
avdd-supply = <&vdd_1v05_run>;
|
|
|
|
target-5v-supply = <&vdd_5v0_sata>;
|
|
target-12v-supply = <&vdd_12v0_sata>;
|
|
};
|
|
|
|
hda@70030000 {
|
|
status = "okay";
|
|
};
|
|
|
|
usb@70090000 {
|
|
phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */
|
|
<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */
|
|
<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */
|
|
<&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */
|
|
phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
|
|
|
|
avddio-pex-supply = <&vdd_1v05_run>;
|
|
dvddio-pex-supply = <&vdd_1v05_run>;
|
|
avdd-usb-supply = <&vdd_3v3_lp0>;
|
|
avdd-pll-utmip-supply = <&vddio_1v8>;
|
|
avdd-pll-erefe-supply = <&avdd_1v05_run>;
|
|
avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
|
|
hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
|
|
hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
|
|
|
|
status = "okay";
|
|
};
|
|
|
|
padctl@7009f000 {
|
|
status = "okay";
|
|
|
|
avdd-pll-utmip-supply = <&vddio_1v8>;
|
|
avdd-pll-erefe-supply = <&avdd_1v05_run>;
|
|
avdd-pex-pll-supply = <&vdd_1v05_run>;
|
|
hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
|
|
|
|
pads {
|
|
usb2 {
|
|
status = "okay";
|
|
|
|
lanes {
|
|
usb2-0 {
|
|
nvidia,function = "snps";
|
|
status = "okay";
|
|
};
|
|
|
|
usb2-1 {
|
|
nvidia,function = "xusb";
|
|
status = "okay";
|
|
};
|
|
|
|
usb2-2 {
|
|
nvidia,function = "xusb";
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie {
|
|
status = "okay";
|
|
|
|
lanes {
|
|
pcie-0 {
|
|
nvidia,function = "usb3-ss";
|
|
status = "okay";
|
|
};
|
|
|
|
pcie-2 {
|
|
nvidia,function = "pcie";
|
|
status = "okay";
|
|
};
|
|
|
|
pcie-4 {
|
|
nvidia,function = "pcie";
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
sata {
|
|
status = "okay";
|
|
|
|
lanes {
|
|
sata-0 {
|
|
nvidia,function = "sata";
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
ports {
|
|
/* Micro A/B */
|
|
usb2-0 {
|
|
status = "okay";
|
|
mode = "host";
|
|
};
|
|
|
|
/* Mini PCIe */
|
|
usb2-1 {
|
|
status = "okay";
|
|
mode = "host";
|
|
};
|
|
|
|
/* USB3 */
|
|
usb2-2 {
|
|
status = "okay";
|
|
mode = "host";
|
|
|
|
vbus-supply = <&vdd_usb3_vbus>;
|
|
};
|
|
|
|
usb3-0 {
|
|
nvidia,usb2-companion = <2>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
/* SD card */
|
|
mmc@700b0400 {
|
|
status = "okay";
|
|
cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
|
|
power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
|
|
wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
|
|
bus-width = <4>;
|
|
vqmmc-supply = <&vddio_sdmmc3>;
|
|
};
|
|
|
|
/* eMMC */
|
|
mmc@700b0600 {
|
|
status = "okay";
|
|
bus-width = <8>;
|
|
non-removable;
|
|
};
|
|
|
|
/* CPU DFLL clock */
|
|
clock@70110000 {
|
|
status = "okay";
|
|
vdd-cpu-supply = <&vdd_cpu>;
|
|
nvidia,i2c-fs-rate = <400000>;
|
|
};
|
|
|
|
ahub@70300000 {
|
|
i2s@70301100 {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
usb@7d000000 {
|
|
compatible = "nvidia,tegra124-udc";
|
|
status = "okay";
|
|
dr_mode = "peripheral";
|
|
};
|
|
|
|
usb-phy@7d000000 {
|
|
status = "okay";
|
|
};
|
|
|
|
/* mini-PCIe USB */
|
|
usb@7d004000 {
|
|
status = "okay";
|
|
};
|
|
|
|
usb-phy@7d004000 {
|
|
status = "okay";
|
|
};
|
|
|
|
/* USB A connector */
|
|
usb@7d008000 {
|
|
status = "okay";
|
|
};
|
|
|
|
usb-phy@7d008000 {
|
|
status = "okay";
|
|
vbus-supply = <&vdd_usb3_vbus>;
|
|
};
|
|
|
|
clk32k_in: clock@0 {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32768>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
cpus {
|
|
cpu@0 {
|
|
vdd-cpu-supply = <&vdd_cpu>;
|
|
};
|
|
};
|
|
|
|
gpio-keys {
|
|
compatible = "gpio-keys";
|
|
|
|
power {
|
|
label = "Power";
|
|
gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
|
|
linux,code = <KEY_POWER>;
|
|
debounce-interval = <10>;
|
|
wakeup-source;
|
|
};
|
|
};
|
|
|
|
vdd_mux: regulator@0 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+VDD_MUX";
|
|
regulator-min-microvolt = <12000000>;
|
|
regulator-max-microvolt = <12000000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
vdd_5v0_sys: regulator@1 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+5V_SYS";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
vin-supply = <&vdd_mux>;
|
|
};
|
|
|
|
vdd_3v3_sys: regulator@2 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+3.3V_SYS";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
vin-supply = <&vdd_mux>;
|
|
};
|
|
|
|
vdd_3v3_run: regulator@3 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+3.3V_RUN";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
vin-supply = <&vdd_3v3_sys>;
|
|
};
|
|
|
|
vdd_3v3_hdmi: regulator@4 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
vin-supply = <&vdd_3v3_run>;
|
|
};
|
|
|
|
vdd_usb1_vbus: regulator@5 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+USB0_VBUS_SW";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
gpio-open-drain;
|
|
vin-supply = <&vdd_5v0_sys>;
|
|
};
|
|
|
|
vdd_usb3_vbus: regulator@6 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+5V_USB_HS";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
gpio-open-drain;
|
|
vin-supply = <&vdd_5v0_sys>;
|
|
};
|
|
|
|
vdd_3v3_lp0: regulator@7 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+3.3V_LP0";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
vin-supply = <&vdd_3v3_sys>;
|
|
};
|
|
|
|
vdd_hdmi_pll: regulator@8 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
|
|
regulator-min-microvolt = <1050000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
|
|
vin-supply = <&vdd_1v05_run>;
|
|
};
|
|
|
|
vdd_5v0_hdmi: regulator@9 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+5V_HDMI_CON";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
vin-supply = <&vdd_5v0_sys>;
|
|
};
|
|
|
|
/* Molex power connector */
|
|
vdd_5v0_sata: regulator@10 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+5V_SATA";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
vin-supply = <&vdd_5v0_sys>;
|
|
};
|
|
|
|
vdd_12v0_sata: regulator@11 {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "+12V_SATA";
|
|
regulator-min-microvolt = <12000000>;
|
|
regulator-max-microvolt = <12000000>;
|
|
gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
vin-supply = <&vdd_mux>;
|
|
};
|
|
|
|
sound {
|
|
compatible = "nvidia,tegra-audio-rt5640-jetson-tk1",
|
|
"nvidia,tegra-audio-rt5640";
|
|
nvidia,model = "NVIDIA Tegra Jetson TK1";
|
|
|
|
nvidia,audio-routing =
|
|
"Headphones", "HPOR",
|
|
"Headphones", "HPOL",
|
|
"Mic Jack", "MICBIAS1",
|
|
"IN2P", "Mic Jack";
|
|
|
|
nvidia,i2s-controller = <&tegra_i2s1>;
|
|
nvidia,audio-codec = <&rt5639>;
|
|
|
|
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>;
|
|
|
|
clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
|
|
<&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
|
|
<&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
|
|
clock-names = "pll_a", "pll_a_out0", "mclk";
|
|
|
|
assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
|
|
<&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
|
|
|
|
assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
|
|
<&tegra_car TEGRA124_CLK_EXTERN1>;
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu {
|
|
trips {
|
|
cpu-shutdown-trip {
|
|
temperature = <101000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
mem {
|
|
trips {
|
|
mem-shutdown-trip {
|
|
temperature = <101000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu {
|
|
trips {
|
|
gpu-shutdown-trip {
|
|
temperature = <101000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|