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a0c4adeeea
ralink,rt2880-uart is compatible with ns16550a and all other instances of RT2880 UART nodes include it in the compatible property. Add it also here, to make the binding schema simpler. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Mans Rullgard <mans@mansr.com> Link: https://lore.kernel.org/r/20200320174107.29406-8-lkundrak@v3.sk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
185 lines
3.8 KiB
Plaintext
185 lines
3.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Based on Mans Rullgard's Tango3 DT
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* https://github.com/mansr/linux-tangox
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define CPU_CLK 0
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#define SYS_CLK 1
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#define USB_CLK 2
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#define SDIO_CLK 3
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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periph_clk: periph_clk {
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compatible = "fixed-factor-clock";
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clocks = <&clkgen CPU_CLK>;
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clock-mult = <1>;
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clock-div = <2>;
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#clock-cells = <0>;
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};
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mpcore {
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compatible = "simple-bus";
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ranges = <0x00000000 0x20000000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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scu@0 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x0 0x100>;
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};
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twd@600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x600 0x10>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
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clocks = <&periph_clk>;
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always-on;
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};
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gic: interrupt-controller@1000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x1000 0x1000>, <0x100 0x100>;
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};
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};
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l2cc: l2-cache-controller@20100000 {
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compatible = "arm,pl310-cache";
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reg = <0x20100000 0x1000>;
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cache-level = <2>;
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cache-unified;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&irq0>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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xtal: xtal {
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compatible = "fixed-clock";
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clock-frequency = <27000000>;
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#clock-cells = <0>;
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};
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clkgen: clkgen@10000 {
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compatible = "sigma,tango4-clkgen";
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reg = <0x10000 0x100>;
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clocks = <&xtal>;
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#clock-cells = <1>;
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};
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tick-counter@10048 {
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compatible = "sigma,tick-counter";
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reg = <0x10048 0x4>;
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clocks = <&xtal>;
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};
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uart: serial@10700 {
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compatible = "ralink,rt2880-uart", "ns16550a";
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reg = <0x10700 0x30>;
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interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <7372800>;
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reg-shift = <2>;
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};
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watchdog@1fd00 {
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compatible = "sigma,smp8759-wdt";
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reg = <0x1fd00 8>;
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clocks = <&xtal>;
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};
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mmc0: mmc@21000 {
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compatible = "arasan,sdhci-8.9a";
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reg = <0x21000 0x200>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clkgen SDIO_CLK>, <&clkgen SYS_CLK>;
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interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
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};
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mmc1: mmc@21200 {
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compatible = "arasan,sdhci-8.9a";
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reg = <0x21200 0x200>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&clkgen SDIO_CLK>, <&clkgen SYS_CLK>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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};
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usb0: usb@21400 {
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compatible = "chipidea,usb2";
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reg = <0x21400 0x200>;
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interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb0_phy>;
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phy-names = "usb-phy";
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};
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usb0_phy: phy@21700 {
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compatible = "sigma,smp8642-usb-phy";
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reg = <0x21700 0x100>;
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#phy-cells = <0>;
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clocks = <&clkgen USB_CLK>;
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};
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usb1: usb@25400 {
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compatible = "chipidea,usb2";
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reg = <0x25400 0x200>;
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interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb1_phy>;
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phy-names = "usb-phy";
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};
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usb1_phy: phy@25700 {
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compatible = "sigma,smp8642-usb-phy";
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reg = <0x25700 0x100>;
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#phy-cells = <0>;
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clocks = <&clkgen USB_CLK>;
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};
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eth0: ethernet@26000 {
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compatible = "sigma,smp8734-ethernet";
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reg = <0x26000 0x800>;
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interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkgen SYS_CLK>;
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};
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intc: interrupt-controller@6e000 {
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compatible = "sigma,smp8642-intc";
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reg = <0x6e000 0x400>;
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ranges = <0 0x6e000 0x400>;
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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irq0: irq0@0 {
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reg = <0x000 0x100>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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};
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irq1: irq1@100 {
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reg = <0x100 0x100>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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};
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irq2: irq2@300 {
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reg = <0x300 0x100>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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};
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