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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 20:16:02 +07:00
8aa937cb4a
The device node for the FIFO-buffered Serial Interface sound node lacks the "clocks" property, as the DTS file didn't describe any clocks yet at its introduction. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200519075525.24742-1-geert+renesas@glider.be
950 lines
27 KiB
Plaintext
950 lines
27 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
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*
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* Copyright (C) 2012 Renesas Solutions Corp.
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*/
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#include <dt-bindings/clock/sh73a0-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "renesas,sh73a0";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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clock-frequency = <1196000000>;
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clocks = <&cpg_clocks SH73A0_CLK_Z>;
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power-domains = <&pd_a2sl>;
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next-level-cache = <&L2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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clock-frequency = <1196000000>;
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clocks = <&cpg_clocks SH73A0_CLK_Z>;
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power-domains = <&pd_a2sl>;
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next-level-cache = <&L2>;
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};
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};
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timer@f0000200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0xf0000200 0x100>;
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interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
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clocks = <&periph_clk>;
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};
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timer@f0000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xf0000600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
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clocks = <&periph_clk>;
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};
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gic: interrupt-controller@f0001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xf0001000 0x1000>,
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<0xf0000100 0x100>;
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};
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L2: cache-controller@f0100000 {
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compatible = "arm,pl310-cache";
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reg = <0xf0100000 0x1000>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&pd_a3sm>;
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arm,data-latency = <3 3 3>;
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arm,tag-latency = <2 2 2>;
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arm,shared-override;
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cache-unified;
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cache-level = <2>;
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};
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sbsc2: memory-controller@fb400000 {
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compatible = "renesas,sbsc-sh73a0";
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reg = <0xfb400000 0x400>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sec", "temp";
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power-domains = <&pd_a4bc1>;
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};
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sbsc1: memory-controller@fe400000 {
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compatible = "renesas,sbsc-sh73a0";
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reg = <0xfe400000 0x400>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sec", "temp";
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power-domains = <&pd_a4bc0>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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cmt1: timer@e6138000 {
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compatible = "renesas,sh73a0-cmt1";
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reg = <0xe6138000 0x200>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
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clock-names = "fck";
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power-domains = <&pd_c5>;
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status = "disabled";
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};
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irqpin0: interrupt-controller@e6900000 {
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compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900000 4>,
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<0xe6900010 4>,
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<0xe6900020 1>,
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<0xe6900040 1>,
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<0xe6900060 1>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
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power-domains = <&pd_a4s>;
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control-parent;
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};
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irqpin1: interrupt-controller@e6900004 {
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compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900004 4>,
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<0xe6900014 4>,
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<0xe6900024 1>,
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<0xe6900044 1>,
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<0xe6900064 1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
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power-domains = <&pd_a4s>;
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control-parent;
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};
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irqpin2: interrupt-controller@e6900008 {
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compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe6900008 4>,
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<0xe6900018 4>,
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<0xe6900028 1>,
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<0xe6900048 1>,
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<0xe6900068 1>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
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power-domains = <&pd_a4s>;
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control-parent;
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};
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irqpin3: interrupt-controller@e690000c {
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compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xe690000c 4>,
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<0xe690001c 4>,
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<0xe690002c 1>,
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<0xe690004c 1>,
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<0xe690006c 1>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
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power-domains = <&pd_a4s>;
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control-parent;
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};
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i2c0: i2c@e6820000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
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reg = <0xe6820000 0x425>;
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interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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i2c1: i2c@e6822000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
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reg = <0xe6822000 0x425>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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i2c2: i2c@e6824000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
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reg = <0xe6824000 0x425>;
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interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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i2c3: i2c@e6826000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
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reg = <0xe6826000 0x425>;
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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i2c4: i2c@e6828000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
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reg = <0xe6828000 0x425>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
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power-domains = <&pd_c5>;
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status = "disabled";
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};
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mmcif: mmc@e6bd0000 {
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compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
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reg = <0xe6bd0000 0x100>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
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power-domains = <&pd_a3sp>;
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reg-io-width = <4>;
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status = "disabled";
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};
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msiof0: spi@e6e20000 {
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compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
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reg = <0xe6e20000 0x0064>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
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power-domains = <&pd_a3sp>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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msiof1: spi@e6e10000 {
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compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
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reg = <0xe6e10000 0x0064>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
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power-domains = <&pd_a3sp>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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msiof2: spi@e6e00000 {
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compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
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reg = <0xe6e00000 0x0064>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
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power-domains = <&pd_a3sp>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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msiof3: spi@e6c90000 {
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compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
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reg = <0xe6c90000 0x0064>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
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power-domains = <&pd_a3sp>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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sdhi0: mmc@ee100000 {
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compatible = "renesas,sdhi-sh73a0";
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reg = <0xee100000 0x100>;
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
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power-domains = <&pd_a3sp>;
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cap-sd-highspeed;
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status = "disabled";
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};
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/* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
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sdhi1: mmc@ee120000 {
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compatible = "renesas,sdhi-sh73a0";
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reg = <0xee120000 0x100>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
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power-domains = <&pd_a3sp>;
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disable-wp;
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cap-sd-highspeed;
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status = "disabled";
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};
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sdhi2: mmc@ee140000 {
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compatible = "renesas,sdhi-sh73a0";
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reg = <0xee140000 0x100>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
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power-domains = <&pd_a3sp>;
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disable-wp;
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cap-sd-highspeed;
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status = "disabled";
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};
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scifa0: serial@e6c40000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c40000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
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clock-names = "fck";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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scifa1: serial@e6c50000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c50000 0x100>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
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clock-names = "fck";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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scifa2: serial@e6c60000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c60000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
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clock-names = "fck";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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scifa3: serial@e6c70000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c70000 0x100>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
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clock-names = "fck";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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scifa4: serial@e6c80000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6c80000 0x100>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
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clock-names = "fck";
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power-domains = <&pd_a3sp>;
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status = "disabled";
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};
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scifa5: serial@e6cb0000 {
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compatible = "renesas,scifa-sh73a0", "renesas,scifa";
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reg = <0xe6cb0000 0x100>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
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clock-names = "fck";
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power-domains = <&pd_a3sp>;
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status = "disabled";
|
|
};
|
|
|
|
scifa6: serial@e6cc0000 {
|
|
compatible = "renesas,scifa-sh73a0", "renesas,scifa";
|
|
reg = <0xe6cc0000 0x100>;
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
|
|
clock-names = "fck";
|
|
power-domains = <&pd_a3sp>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifa7: serial@e6cd0000 {
|
|
compatible = "renesas,scifa-sh73a0", "renesas,scifa";
|
|
reg = <0xe6cd0000 0x100>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
|
|
clock-names = "fck";
|
|
power-domains = <&pd_a3sp>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scifb: serial@e6c30000 {
|
|
compatible = "renesas,scifb-sh73a0", "renesas,scifb";
|
|
reg = <0xe6c30000 0x100>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
|
|
clock-names = "fck";
|
|
power-domains = <&pd_a3sp>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pfc: pin-controller@e6050000 {
|
|
compatible = "renesas,pfc-sh73a0";
|
|
reg = <0xe6050000 0x8000>,
|
|
<0xe605801c 0x1c>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges =
|
|
<&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
|
|
<&pfc 288 288 22>;
|
|
interrupts-extended =
|
|
<&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
|
|
<&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
|
|
<&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
|
|
<&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
|
|
<&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
|
|
<&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
|
|
<&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
|
|
<&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
|
|
power-domains = <&pd_c5>;
|
|
};
|
|
|
|
sysc: system-controller@e6180000 {
|
|
compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
|
|
reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
|
|
|
|
pm-domains {
|
|
pd_c5: c5 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <0>;
|
|
|
|
pd_c4: c4@0 {
|
|
reg = <0>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_d4: d4@1 {
|
|
reg = <1>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_a4bc0: a4bc0@4 {
|
|
reg = <4>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_a4bc1: a4bc1@5 {
|
|
reg = <5>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_a4lc0: a4lc0@6 {
|
|
reg = <6>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_a4lc1: a4lc1@7 {
|
|
reg = <7>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_a4mp: a4mp@8 {
|
|
reg = <8>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <0>;
|
|
|
|
pd_a3mp: a3mp@9 {
|
|
reg = <9>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_a3vc: a3vc@10 {
|
|
reg = <10>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
};
|
|
|
|
pd_a4rm: a4rm@12 {
|
|
reg = <12>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <0>;
|
|
|
|
pd_a3r: a3r@13 {
|
|
reg = <13>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <0>;
|
|
|
|
pd_a2rv: a2rv@14 {
|
|
reg = <14>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pd_a4s: a4s@16 {
|
|
reg = <16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <0>;
|
|
|
|
pd_a3sp: a3sp@17 {
|
|
reg = <17>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_a3sg: a3sg@18 {
|
|
reg = <18>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
pd_a3sm: a3sm@19 {
|
|
reg = <19>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#power-domain-cells = <0>;
|
|
|
|
pd_a2sl: a2sl@20 {
|
|
reg = <20>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
sh_fsi2: sound@ec230000 {
|
|
#sound-dai-cells = <1>;
|
|
compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
|
|
reg = <0xec230000 0x400>;
|
|
interrupts = <GIC_SPI 146 0x4>;
|
|
clocks = <&mstp3_clks SH73A0_CLK_FSI>;
|
|
power-domains = <&pd_a4mp>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bsc: bus@fec10000 {
|
|
compatible = "renesas,bsc-sh73a0", "renesas,bsc",
|
|
"simple-pm-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0x20000000>;
|
|
reg = <0xfec10000 0x400>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&zb_clk>;
|
|
power-domains = <&pd_a4s>;
|
|
};
|
|
|
|
clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
/* External root clocks */
|
|
extalr_clk: extalr {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
extal1_clk: extal1 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <26000000>;
|
|
};
|
|
extal2_clk: extal2 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overridden by the board. */
|
|
clock-frequency = <0>;
|
|
};
|
|
extcki_clk: extcki {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value can be overridden by the board. */
|
|
clock-frequency = <0>;
|
|
};
|
|
fsiack_clk: fsiack {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value can be overridden by the board. */
|
|
clock-frequency = <0>;
|
|
};
|
|
fsibck_clk: fsibck {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value can be overridden by the board. */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
/* Special CPG clocks */
|
|
cpg_clocks: cpg_clocks@e6150000 {
|
|
compatible = "renesas,sh73a0-cpg-clocks";
|
|
reg = <0xe6150000 0x10000>;
|
|
clocks = <&extal1_clk>, <&extal2_clk>;
|
|
#clock-cells = <1>;
|
|
clock-output-names = "main", "pll0", "pll1", "pll2",
|
|
"pll3", "dsi0phy", "dsi1phy",
|
|
"zg", "m3", "b", "m1", "m2",
|
|
"z", "zx", "hp";
|
|
};
|
|
|
|
/* Variable factor clocks (DIV6) */
|
|
vclk1_clk: vclk1@e6150008 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150008 4>;
|
|
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
|
<&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
|
|
<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
|
|
<0>;
|
|
#clock-cells = <0>;
|
|
};
|
|
vclk2_clk: vclk2@e615000c {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe615000c 4>;
|
|
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
|
<&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
|
|
<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
|
|
<0>;
|
|
#clock-cells = <0>;
|
|
};
|
|
vclk3_clk: vclk3@e615001c {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe615001c 4>;
|
|
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
|
<&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
|
|
<&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
|
|
<0>;
|
|
#clock-cells = <0>;
|
|
};
|
|
zb_clk: zb_clk@e6150010 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150010 4>;
|
|
clocks = <&pll1_div2_clk>, <0>,
|
|
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "zb";
|
|
};
|
|
flctl_clk: flctlck@e6150014 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150014 4>;
|
|
clocks = <&pll1_div2_clk>, <0>,
|
|
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
|
|
#clock-cells = <0>;
|
|
};
|
|
sdhi0_clk: sdhi0ck@e6150074 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150074 4>;
|
|
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
|
<&pll1_div13_clk>, <0>;
|
|
#clock-cells = <0>;
|
|
};
|
|
sdhi1_clk: sdhi1ck@e6150078 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150078 4>;
|
|
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
|
<&pll1_div13_clk>, <0>;
|
|
#clock-cells = <0>;
|
|
};
|
|
sdhi2_clk: sdhi2ck@e615007c {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe615007c 4>;
|
|
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
|
<&pll1_div13_clk>, <0>;
|
|
#clock-cells = <0>;
|
|
};
|
|
fsia_clk: fsia@e6150018 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150018 4>;
|
|
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
|
<&fsiack_clk>, <&fsiack_clk>;
|
|
#clock-cells = <0>;
|
|
};
|
|
fsib_clk: fsib@e6150090 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150090 4>;
|
|
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
|
<&fsibck_clk>, <&fsibck_clk>;
|
|
#clock-cells = <0>;
|
|
};
|
|
sub_clk: sub@e6150080 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150080 4>;
|
|
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
|
<&extal2_clk>, <&extal2_clk>;
|
|
#clock-cells = <0>;
|
|
};
|
|
spua_clk: spua@e6150084 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150084 4>;
|
|
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
|
<&extal2_clk>, <&extal2_clk>;
|
|
#clock-cells = <0>;
|
|
};
|
|
spuv_clk: spuv@e6150094 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150094 4>;
|
|
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
|
<&extal2_clk>, <&extal2_clk>;
|
|
#clock-cells = <0>;
|
|
};
|
|
msu_clk: msu@e6150088 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150088 4>;
|
|
clocks = <&pll1_div2_clk>, <0>,
|
|
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
|
|
#clock-cells = <0>;
|
|
};
|
|
hsi_clk: hsi@e615008c {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe615008c 4>;
|
|
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
|
<&pll1_div7_clk>, <0>;
|
|
#clock-cells = <0>;
|
|
};
|
|
mfg1_clk: mfg1@e6150098 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150098 4>;
|
|
clocks = <&pll1_div2_clk>, <0>,
|
|
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
|
|
#clock-cells = <0>;
|
|
};
|
|
mfg2_clk: mfg2@e615009c {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe615009c 4>;
|
|
clocks = <&pll1_div2_clk>, <0>,
|
|
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
|
|
#clock-cells = <0>;
|
|
};
|
|
dsit_clk: dsit@e6150060 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150060 4>;
|
|
clocks = <&pll1_div2_clk>, <0>,
|
|
<&cpg_clocks SH73A0_CLK_PLL2>, <0>;
|
|
#clock-cells = <0>;
|
|
};
|
|
dsi0p_clk: dsi0pck@e6150064 {
|
|
compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
|
|
reg = <0xe6150064 4>;
|
|
clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
|
|
<&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
|
|
<&extcki_clk>, <0>, <0>, <0>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
/* Fixed factor clocks */
|
|
main_div2_clk: main_div2 {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
};
|
|
pll1_div2_clk: pll1_div2 {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <2>;
|
|
clock-mult = <1>;
|
|
};
|
|
pll1_div7_clk: pll1_div7 {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <7>;
|
|
clock-mult = <1>;
|
|
};
|
|
pll1_div13_clk: pll1_div13 {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
|
|
#clock-cells = <0>;
|
|
clock-div = <13>;
|
|
clock-mult = <1>;
|
|
};
|
|
periph_clk: periph {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&cpg_clocks SH73A0_CLK_Z>;
|
|
#clock-cells = <0>;
|
|
clock-div = <4>;
|
|
clock-mult = <1>;
|
|
};
|
|
|
|
/* Gate clocks */
|
|
mstp0_clks: mstp0_clks@e6150130 {
|
|
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0xe6150130 4>, <0xe6150030 4>;
|
|
clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
|
|
>;
|
|
clock-output-names =
|
|
"iic2", "msiof0";
|
|
};
|
|
mstp1_clks: mstp1_clks@e6150134 {
|
|
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0xe6150134 4>, <0xe6150038 4>;
|
|
clocks = <&cpg_clocks SH73A0_CLK_B>,
|
|
<&cpg_clocks SH73A0_CLK_B>,
|
|
<&cpg_clocks SH73A0_CLK_B>,
|
|
<&cpg_clocks SH73A0_CLK_B>,
|
|
<&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
|
|
<&cpg_clocks SH73A0_CLK_HP>,
|
|
<&cpg_clocks SH73A0_CLK_ZG>,
|
|
<&cpg_clocks SH73A0_CLK_B>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
|
|
SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
|
|
SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
|
|
SH73A0_CLK_IIC0 SH73A0_CLK_SGX
|
|
SH73A0_CLK_LCDC0
|
|
>;
|
|
clock-output-names =
|
|
"ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
|
|
"tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
|
|
};
|
|
mstp2_clks: mstp2_clks@e6150138 {
|
|
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0xe6150138 4>, <0xe6150040 4>;
|
|
clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
|
|
<&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
|
|
<&sub_clk>, <&sub_clk>, <&sub_clk>,
|
|
<&sub_clk>, <&sub_clk>, <&sub_clk>,
|
|
<&sub_clk>, <&sub_clk>, <&sub_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
|
|
SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
|
|
SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
|
|
SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
|
|
SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
|
|
SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
|
|
SH73A0_CLK_SCIFA4
|
|
>;
|
|
clock-output-names =
|
|
"scifa7", "sy_dmac", "mp_dmac", "msiof3",
|
|
"msiof1", "scifa5", "scifb", "msiof2",
|
|
"scifa0", "scifa1", "scifa2", "scifa3",
|
|
"scifa4";
|
|
};
|
|
mstp3_clks: mstp3_clks@e615013c {
|
|
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0xe615013c 4>, <0xe6150048 4>;
|
|
clocks = <&sub_clk>, <&extalr_clk>,
|
|
<&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
|
|
<&cpg_clocks SH73A0_CLK_HP>,
|
|
<&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
|
|
<&sdhi0_clk>, <&sdhi1_clk>,
|
|
<&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
|
|
<&main_div2_clk>, <&main_div2_clk>,
|
|
<&main_div2_clk>, <&main_div2_clk>,
|
|
<&main_div2_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
|
|
SH73A0_CLK_FSI SH73A0_CLK_IRDA
|
|
SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
|
|
SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
|
|
SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
|
|
SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
|
|
SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
|
|
SH73A0_CLK_TPU4
|
|
>;
|
|
clock-output-names =
|
|
"scifa6", "cmt1", "fsi", "irda", "iic1",
|
|
"usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
|
|
"tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
|
|
};
|
|
mstp4_clks: mstp4_clks@e6150140 {
|
|
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0xe6150140 4>, <0xe615004c 4>;
|
|
clocks = <&cpg_clocks SH73A0_CLK_HP>,
|
|
<&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
|
|
SH73A0_CLK_KEYSC
|
|
>;
|
|
clock-output-names =
|
|
"iic3", "iic4", "keysc";
|
|
};
|
|
mstp5_clks: mstp5_clks@e6150144 {
|
|
compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
|
|
reg = <0xe6150144 4>, <0xe615003c 4>;
|
|
clocks = <&cpg_clocks SH73A0_CLK_HP>;
|
|
#clock-cells = <1>;
|
|
clock-indices = <
|
|
SH73A0_CLK_INTCA0
|
|
>;
|
|
clock-output-names =
|
|
"intca0";
|
|
};
|
|
};
|
|
};
|