mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-23 22:20:01 +07:00
7128d7f7ba
i.MX7ULP has a Cortex-A7 CPU which can run in RUN mode
or HSRUN mode, it is controlled in SMC1 module. The RUN
mode and HSRUN mode will use different clock source for
ARM, "divcore" for RUN mode and "hsrun_divcore" for HSRUN
mode, so the control bits in SMC1 module can be abstracted
as a HW clock mux, this patch adds HSRUN mode related
clocks in SCG1 module and adds "arm" clock in SMC1 module
to support RUN mode and HSRUN mode switch.
Latest clock tree in RUN mode as below:
firc 0 0 0 48000000 0 0 50000
firc_bus_clk 0 0 0 48000000 0 0 50000
hsrun_scs_sel 0 0 0 48000000 0 0 50000
hsrun_divcore 0 0 0 48000000 0 0 50000
sosc 3 3 3 24000000 0 0 50000
spll_pre_sel 1 1 1 24000000 0 0 50000
spll_pre_div 1 1 2 24000000 0 0 50000
spll 1 1 2 528000000 0 0 50000
spll_pfd0 1 1 1 500210526 0 0 50000
spll_pfd_sel 1 1 0 500210526 0 0 50000
spll_sel 1 1 0 500210526 0 0 50000
scs_sel 1 1 0 500210526 0 0 50000
divcore 1 1 0 500210526 0 0 50000
arm 1 1 0 500210526 0 0 50000
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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|---|---|---|
| .. | ||
| clk-busy.c | ||
| clk-composite-7ulp.c | ||
| clk-cpu.c | ||
| clk-divider-gate.c | ||
| clk-fixup-div.c | ||
| clk-fixup-mux.c | ||
| clk-gate2.c | ||
| clk-gate-exclusive.c | ||
| clk-imx1.c | ||
| clk-imx6q.c | ||
| clk-imx6sl.c | ||
| clk-imx6sll.c | ||
| clk-imx6sx.c | ||
| clk-imx6ul.c | ||
| clk-imx7d.c | ||
| clk-imx7ulp.c | ||
| clk-imx21.c | ||
| clk-imx25.c | ||
| clk-imx27.c | ||
| clk-imx31.c | ||
| clk-imx35.c | ||
| clk-imx51-imx53.c | ||
| clk-pfd.c | ||
| clk-pfdv2.c | ||
| clk-pllv1.c | ||
| clk-pllv2.c | ||
| clk-pllv3.c | ||
| clk-pllv4.c | ||
| clk-vf610.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||