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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b229632abd
Mostly SH-2 wrappers.. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
85 lines
1.9 KiB
C
85 lines
1.9 KiB
C
#ifndef __ASM_SH_CPU_SH2_IRQ_H
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#define __ASM_SH_CPU_SH2_IRQ_H
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/*
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*
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* linux/include/asm-sh/cpu-sh2/irq.h
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2003 Paul Mundt
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*
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*/
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#include <linux/config.h>
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#if defined(CONFIG_CPU_SUBTYPE_SH7044)
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#define INTC_IPRA 0xffff8348UL
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#define INTC_IPRB 0xffff834aUL
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#define INTC_IPRC 0xffff834cUL
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#define INTC_IPRD 0xffff834eUL
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#define INTC_IPRE 0xffff8350UL
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#define INTC_IPRF 0xffff8352UL
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#define INTC_IPRG 0xffff8354UL
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#define INTC_IPRH 0xffff8356UL
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#define INTC_ICR 0xffff8358UL
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#define INTC_ISR 0xffff835aUL
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#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
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#define INTC_IPRA 0xfffffee2UL
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#define INTC_IPRB 0xfffffe60UL
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#define INTC_VCRA 0xfffffe62UL
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#define INTC_VCRB 0xfffffe64UL
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#define INTC_VCRC 0xfffffe66UL
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#define INTC_VCRD 0xfffffe68UL
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#define INTC_VCRWDT 0xfffffee4UL
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#define INTC_VCRDIV 0xffffff0cUL
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#define INTC_VCRDMA0 0xffffffa0UL
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#define INTC_VCRDMA1 0xffffffa8UL
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#define INTC_ICR 0xfffffee0UL
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#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
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#define INTC_IPRA 0xf8140006UL
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#define INTC_IPRB 0xf8140008UL
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#define INTC_IPRC 0xf8080000UL
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#define INTC_IPRD 0xf8080002UL
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#define INTC_IPRE 0xf8080004UL
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#define INTC_IPRF 0xf8080006UL
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#define INTC_IPRG 0xf8080008UL
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#define INTC_ICR0 0xf8140000UL
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#define INTC_IRQCR 0xf8140002UL
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#define INTC_IRQSR 0xf8140004UL
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#define CMI0_IRQ 86
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#define CMI1_IRQ 87
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#define SCIF_ERI_IRQ 88
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#define SCIF_RXI_IRQ 89
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#define SCIF_BRI_IRQ 90
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#define SCIF_TXI_IRQ 91
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#define SCIF_IPR_ADDR INTC_IPRD
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#define SCIF_IPR_POS 3
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#define SCIF_PRIORITY 3
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#define SCIF1_ERI_IRQ 92
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#define SCIF1_RXI_IRQ 93
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#define SCIF1_BRI_IRQ 94
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#define SCIF1_TXI_IRQ 95
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#define SCIF1_IPR_ADDR INTC_IPRD
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#define SCIF1_IPR_POS 2
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#define SCIF1_PRIORITY 3
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#define SCIF2_BRI_IRQ 96
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#define SCIF2_RXI_IRQ 97
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#define SCIF2_ERI_IRQ 98
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#define SCIF2_TXI_IRQ 99
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#define SCIF2_IPR_ADDR INTC_IPRD
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#define SCIF2_IPR_POS 1
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#define SCIF2_PRIORITY 3
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#endif
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#endif /* __ASM_SH_CPU_SH2_IRQ_H */
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