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689dc64385
According to the spec, the definition of TDM and ONELINE_24 for CS42XX8_INTF_DAC and CS42XX8_INTF_ADC is wrong. correct them and enable SND_SOC_DAIFMT_DSP_A support. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Acked-by: Brian Austin <brian.austin@cirrus.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
239 lines
13 KiB
C
239 lines
13 KiB
C
/*
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* cs42xx8.h - Cirrus Logic CS42448/CS42888 Audio CODEC driver header file
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*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* Author: Nicolin Chen <Guangyu.Chen@freescale.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#ifndef _CS42XX8_H
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#define _CS42XX8_H
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struct cs42xx8_driver_data {
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char name[32];
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int num_adcs;
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};
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extern const struct dev_pm_ops cs42xx8_pm;
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extern const struct cs42xx8_driver_data cs42448_data;
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extern const struct cs42xx8_driver_data cs42888_data;
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extern const struct regmap_config cs42xx8_regmap_config;
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int cs42xx8_probe(struct device *dev, struct regmap *regmap);
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/* CS42888 register map */
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#define CS42XX8_CHIPID 0x01 /* Chip ID */
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#define CS42XX8_PWRCTL 0x02 /* Power Control */
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#define CS42XX8_FUNCMOD 0x03 /* Functional Mode */
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#define CS42XX8_INTF 0x04 /* Interface Formats */
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#define CS42XX8_ADCCTL 0x05 /* ADC Control */
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#define CS42XX8_TXCTL 0x06 /* Transition Control */
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#define CS42XX8_DACMUTE 0x07 /* DAC Mute Control */
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#define CS42XX8_VOLAOUT1 0x08 /* Volume Control AOUT1 */
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#define CS42XX8_VOLAOUT2 0x09 /* Volume Control AOUT2 */
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#define CS42XX8_VOLAOUT3 0x0A /* Volume Control AOUT3 */
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#define CS42XX8_VOLAOUT4 0x0B /* Volume Control AOUT4 */
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#define CS42XX8_VOLAOUT5 0x0C /* Volume Control AOUT5 */
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#define CS42XX8_VOLAOUT6 0x0D /* Volume Control AOUT6 */
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#define CS42XX8_VOLAOUT7 0x0E /* Volume Control AOUT7 */
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#define CS42XX8_VOLAOUT8 0x0F /* Volume Control AOUT8 */
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#define CS42XX8_DACINV 0x10 /* DAC Channel Invert */
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#define CS42XX8_VOLAIN1 0x11 /* Volume Control AIN1 */
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#define CS42XX8_VOLAIN2 0x12 /* Volume Control AIN2 */
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#define CS42XX8_VOLAIN3 0x13 /* Volume Control AIN3 */
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#define CS42XX8_VOLAIN4 0x14 /* Volume Control AIN4 */
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#define CS42XX8_VOLAIN5 0x15 /* Volume Control AIN5 */
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#define CS42XX8_VOLAIN6 0x16 /* Volume Control AIN6 */
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#define CS42XX8_ADCINV 0x17 /* ADC Channel Invert */
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#define CS42XX8_STATUSCTL 0x18 /* Status Control */
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#define CS42XX8_STATUS 0x19 /* Status */
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#define CS42XX8_STATUSM 0x1A /* Status Mask */
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#define CS42XX8_MUTEC 0x1B /* MUTEC Pin Control */
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#define CS42XX8_FIRSTREG CS42XX8_CHIPID
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#define CS42XX8_LASTREG CS42XX8_MUTEC
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#define CS42XX8_NUMREGS (CS42XX8_LASTREG - CS42XX8_FIRSTREG + 1)
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#define CS42XX8_I2C_INCR 0x80
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/* Chip I.D. and Revision Register (Address 01h) */
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#define CS42XX8_CHIPID_CHIP_ID_MASK 0xF0
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#define CS42XX8_CHIPID_REV_ID_MASK 0x0F
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/* Power Control (Address 02h) */
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#define CS42XX8_PWRCTL_PDN_ADC3_SHIFT 7
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#define CS42XX8_PWRCTL_PDN_ADC3_MASK (1 << CS42XX8_PWRCTL_PDN_ADC3_SHIFT)
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#define CS42XX8_PWRCTL_PDN_ADC3 (1 << CS42XX8_PWRCTL_PDN_ADC3_SHIFT)
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#define CS42XX8_PWRCTL_PDN_ADC2_SHIFT 6
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#define CS42XX8_PWRCTL_PDN_ADC2_MASK (1 << CS42XX8_PWRCTL_PDN_ADC2_SHIFT)
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#define CS42XX8_PWRCTL_PDN_ADC2 (1 << CS42XX8_PWRCTL_PDN_ADC2_SHIFT)
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#define CS42XX8_PWRCTL_PDN_ADC1_SHIFT 5
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#define CS42XX8_PWRCTL_PDN_ADC1_MASK (1 << CS42XX8_PWRCTL_PDN_ADC1_SHIFT)
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#define CS42XX8_PWRCTL_PDN_ADC1 (1 << CS42XX8_PWRCTL_PDN_ADC1_SHIFT)
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#define CS42XX8_PWRCTL_PDN_DAC4_SHIFT 4
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#define CS42XX8_PWRCTL_PDN_DAC4_MASK (1 << CS42XX8_PWRCTL_PDN_DAC4_SHIFT)
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#define CS42XX8_PWRCTL_PDN_DAC4 (1 << CS42XX8_PWRCTL_PDN_DAC4_SHIFT)
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#define CS42XX8_PWRCTL_PDN_DAC3_SHIFT 3
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#define CS42XX8_PWRCTL_PDN_DAC3_MASK (1 << CS42XX8_PWRCTL_PDN_DAC3_SHIFT)
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#define CS42XX8_PWRCTL_PDN_DAC3 (1 << CS42XX8_PWRCTL_PDN_DAC3_SHIFT)
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#define CS42XX8_PWRCTL_PDN_DAC2_SHIFT 2
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#define CS42XX8_PWRCTL_PDN_DAC2_MASK (1 << CS42XX8_PWRCTL_PDN_DAC2_SHIFT)
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#define CS42XX8_PWRCTL_PDN_DAC2 (1 << CS42XX8_PWRCTL_PDN_DAC2_SHIFT)
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#define CS42XX8_PWRCTL_PDN_DAC1_SHIFT 1
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#define CS42XX8_PWRCTL_PDN_DAC1_MASK (1 << CS42XX8_PWRCTL_PDN_DAC1_SHIFT)
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#define CS42XX8_PWRCTL_PDN_DAC1 (1 << CS42XX8_PWRCTL_PDN_DAC1_SHIFT)
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#define CS42XX8_PWRCTL_PDN_SHIFT 0
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#define CS42XX8_PWRCTL_PDN_MASK (1 << CS42XX8_PWRCTL_PDN_SHIFT)
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#define CS42XX8_PWRCTL_PDN (1 << CS42XX8_PWRCTL_PDN_SHIFT)
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/* Functional Mode (Address 03h) */
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#define CS42XX8_FUNCMOD_DAC_FM_SHIFT 6
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#define CS42XX8_FUNCMOD_DAC_FM_WIDTH 2
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#define CS42XX8_FUNCMOD_DAC_FM_MASK (((1 << CS42XX8_FUNCMOD_DAC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_DAC_FM_SHIFT)
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#define CS42XX8_FUNCMOD_DAC_FM(v) ((v) << CS42XX8_FUNCMOD_DAC_FM_SHIFT)
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#define CS42XX8_FUNCMOD_ADC_FM_SHIFT 4
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#define CS42XX8_FUNCMOD_ADC_FM_WIDTH 2
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#define CS42XX8_FUNCMOD_ADC_FM_MASK (((1 << CS42XX8_FUNCMOD_ADC_FM_WIDTH) - 1) << CS42XX8_FUNCMOD_ADC_FM_SHIFT)
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#define CS42XX8_FUNCMOD_ADC_FM(v) ((v) << CS42XX8_FUNCMOD_ADC_FM_SHIFT)
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#define CS42XX8_FUNCMOD_xC_FM_MASK(x) ((x) ? CS42XX8_FUNCMOD_DAC_FM_MASK : CS42XX8_FUNCMOD_ADC_FM_MASK)
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#define CS42XX8_FUNCMOD_xC_FM(x, v) ((x) ? CS42XX8_FUNCMOD_DAC_FM(v) : CS42XX8_FUNCMOD_ADC_FM(v))
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#define CS42XX8_FUNCMOD_MFREQ_SHIFT 1
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#define CS42XX8_FUNCMOD_MFREQ_WIDTH 3
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#define CS42XX8_FUNCMOD_MFREQ_MASK (((1 << CS42XX8_FUNCMOD_MFREQ_WIDTH) - 1) << CS42XX8_FUNCMOD_MFREQ_SHIFT)
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#define CS42XX8_FUNCMOD_MFREQ_256(s) ((0 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
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#define CS42XX8_FUNCMOD_MFREQ_384(s) ((1 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
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#define CS42XX8_FUNCMOD_MFREQ_512(s) ((2 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
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#define CS42XX8_FUNCMOD_MFREQ_768(s) ((3 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
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#define CS42XX8_FUNCMOD_MFREQ_1024(s) ((4 << CS42XX8_FUNCMOD_MFREQ_SHIFT) >> (s >> 1))
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#define CS42XX8_FM_SINGLE 0
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#define CS42XX8_FM_DOUBLE 1
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#define CS42XX8_FM_QUAD 2
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#define CS42XX8_FM_AUTO 3
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/* Interface Formats (Address 04h) */
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#define CS42XX8_INTF_FREEZE_SHIFT 7
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#define CS42XX8_INTF_FREEZE_MASK (1 << CS42XX8_INTF_FREEZE_SHIFT)
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#define CS42XX8_INTF_FREEZE (1 << CS42XX8_INTF_FREEZE_SHIFT)
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#define CS42XX8_INTF_AUX_DIF_SHIFT 6
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#define CS42XX8_INTF_AUX_DIF_MASK (1 << CS42XX8_INTF_AUX_DIF_SHIFT)
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#define CS42XX8_INTF_AUX_DIF (1 << CS42XX8_INTF_AUX_DIF_SHIFT)
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#define CS42XX8_INTF_DAC_DIF_SHIFT 3
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#define CS42XX8_INTF_DAC_DIF_WIDTH 3
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#define CS42XX8_INTF_DAC_DIF_MASK (((1 << CS42XX8_INTF_DAC_DIF_WIDTH) - 1) << CS42XX8_INTF_DAC_DIF_SHIFT)
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#define CS42XX8_INTF_DAC_DIF_LEFTJ (0 << CS42XX8_INTF_DAC_DIF_SHIFT)
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#define CS42XX8_INTF_DAC_DIF_I2S (1 << CS42XX8_INTF_DAC_DIF_SHIFT)
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#define CS42XX8_INTF_DAC_DIF_RIGHTJ (2 << CS42XX8_INTF_DAC_DIF_SHIFT)
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#define CS42XX8_INTF_DAC_DIF_RIGHTJ_16 (3 << CS42XX8_INTF_DAC_DIF_SHIFT)
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#define CS42XX8_INTF_DAC_DIF_ONELINE_20 (4 << CS42XX8_INTF_DAC_DIF_SHIFT)
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#define CS42XX8_INTF_DAC_DIF_ONELINE_24 (5 << CS42XX8_INTF_DAC_DIF_SHIFT)
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#define CS42XX8_INTF_DAC_DIF_TDM (6 << CS42XX8_INTF_DAC_DIF_SHIFT)
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#define CS42XX8_INTF_ADC_DIF_SHIFT 0
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#define CS42XX8_INTF_ADC_DIF_WIDTH 3
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#define CS42XX8_INTF_ADC_DIF_MASK (((1 << CS42XX8_INTF_ADC_DIF_WIDTH) - 1) << CS42XX8_INTF_ADC_DIF_SHIFT)
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#define CS42XX8_INTF_ADC_DIF_LEFTJ (0 << CS42XX8_INTF_ADC_DIF_SHIFT)
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#define CS42XX8_INTF_ADC_DIF_I2S (1 << CS42XX8_INTF_ADC_DIF_SHIFT)
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#define CS42XX8_INTF_ADC_DIF_RIGHTJ (2 << CS42XX8_INTF_ADC_DIF_SHIFT)
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#define CS42XX8_INTF_ADC_DIF_RIGHTJ_16 (3 << CS42XX8_INTF_ADC_DIF_SHIFT)
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#define CS42XX8_INTF_ADC_DIF_ONELINE_20 (4 << CS42XX8_INTF_ADC_DIF_SHIFT)
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#define CS42XX8_INTF_ADC_DIF_ONELINE_24 (5 << CS42XX8_INTF_ADC_DIF_SHIFT)
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#define CS42XX8_INTF_ADC_DIF_TDM (6 << CS42XX8_INTF_ADC_DIF_SHIFT)
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/* ADC Control & DAC De-Emphasis (Address 05h) */
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#define CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT 7
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#define CS42XX8_ADCCTL_ADC_HPF_FREEZE_MASK (1 << CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT)
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#define CS42XX8_ADCCTL_ADC_HPF_FREEZE (1 << CS42XX8_ADCCTL_ADC_HPF_FREEZE_SHIFT)
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#define CS42XX8_ADCCTL_DAC_DEM_SHIFT 5
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#define CS42XX8_ADCCTL_DAC_DEM_MASK (1 << CS42XX8_ADCCTL_DAC_DEM_SHIFT)
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#define CS42XX8_ADCCTL_DAC_DEM (1 << CS42XX8_ADCCTL_DAC_DEM_SHIFT)
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#define CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT 4
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#define CS42XX8_ADCCTL_ADC1_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT)
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#define CS42XX8_ADCCTL_ADC1_SINGLE (1 << CS42XX8_ADCCTL_ADC1_SINGLE_SHIFT)
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#define CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT 3
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#define CS42XX8_ADCCTL_ADC2_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT)
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#define CS42XX8_ADCCTL_ADC2_SINGLE (1 << CS42XX8_ADCCTL_ADC2_SINGLE_SHIFT)
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#define CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT 2
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#define CS42XX8_ADCCTL_ADC3_SINGLE_MASK (1 << CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT)
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#define CS42XX8_ADCCTL_ADC3_SINGLE (1 << CS42XX8_ADCCTL_ADC3_SINGLE_SHIFT)
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#define CS42XX8_ADCCTL_AIN5_MUX_SHIFT 1
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#define CS42XX8_ADCCTL_AIN5_MUX_MASK (1 << CS42XX8_ADCCTL_AIN5_MUX_SHIFT)
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#define CS42XX8_ADCCTL_AIN5_MUX (1 << CS42XX8_ADCCTL_AIN5_MUX_SHIFT)
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#define CS42XX8_ADCCTL_AIN6_MUX_SHIFT 0
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#define CS42XX8_ADCCTL_AIN6_MUX_MASK (1 << CS42XX8_ADCCTL_AIN6_MUX_SHIFT)
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#define CS42XX8_ADCCTL_AIN6_MUX (1 << CS42XX8_ADCCTL_AIN6_MUX_SHIFT)
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/* Transition Control (Address 06h) */
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#define CS42XX8_TXCTL_DAC_SNGVOL_SHIFT 7
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#define CS42XX8_TXCTL_DAC_SNGVOL_MASK (1 << CS42XX8_TXCTL_DAC_SNGVOL_SHIFT)
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#define CS42XX8_TXCTL_DAC_SNGVOL (1 << CS42XX8_TXCTL_DAC_SNGVOL_SHIFT)
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#define CS42XX8_TXCTL_DAC_SZC_SHIFT 5
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#define CS42XX8_TXCTL_DAC_SZC_WIDTH 2
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#define CS42XX8_TXCTL_DAC_SZC_MASK (((1 << CS42XX8_TXCTL_DAC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_DAC_SZC_SHIFT)
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#define CS42XX8_TXCTL_DAC_SZC_IC (0 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
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#define CS42XX8_TXCTL_DAC_SZC_ZC (1 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
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#define CS42XX8_TXCTL_DAC_SZC_SR (2 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
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#define CS42XX8_TXCTL_DAC_SZC_SRZC (3 << CS42XX8_TXCTL_DAC_SZC_SHIFT)
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#define CS42XX8_TXCTL_AMUTE_SHIFT 4
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#define CS42XX8_TXCTL_AMUTE_MASK (1 << CS42XX8_TXCTL_AMUTE_SHIFT)
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#define CS42XX8_TXCTL_AMUTE (1 << CS42XX8_TXCTL_AMUTE_SHIFT)
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#define CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT 3
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#define CS42XX8_TXCTL_MUTE_ADC_SP_MASK (1 << CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT)
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#define CS42XX8_TXCTL_MUTE_ADC_SP (1 << CS42XX8_TXCTL_MUTE_ADC_SP_SHIFT)
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#define CS42XX8_TXCTL_ADC_SNGVOL_SHIFT 2
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#define CS42XX8_TXCTL_ADC_SNGVOL_MASK (1 << CS42XX8_TXCTL_ADC_SNGVOL_SHIFT)
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#define CS42XX8_TXCTL_ADC_SNGVOL (1 << CS42XX8_TXCTL_ADC_SNGVOL_SHIFT)
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#define CS42XX8_TXCTL_ADC_SZC_SHIFT 0
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#define CS42XX8_TXCTL_ADC_SZC_MASK (((1 << CS42XX8_TXCTL_ADC_SZC_WIDTH) - 1) << CS42XX8_TXCTL_ADC_SZC_SHIFT)
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#define CS42XX8_TXCTL_ADC_SZC_IC (0 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
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#define CS42XX8_TXCTL_ADC_SZC_ZC (1 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
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#define CS42XX8_TXCTL_ADC_SZC_SR (2 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
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#define CS42XX8_TXCTL_ADC_SZC_SRZC (3 << CS42XX8_TXCTL_ADC_SZC_SHIFT)
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/* DAC Channel Mute (Address 07h) */
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#define CS42XX8_DACMUTE_AOUT(n) (0x1 << n)
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#define CS42XX8_DACMUTE_ALL 0xff
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/* Status Control (Address 18h)*/
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#define CS42XX8_STATUSCTL_INI_SHIFT 2
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#define CS42XX8_STATUSCTL_INI_WIDTH 2
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#define CS42XX8_STATUSCTL_INI_MASK (((1 << CS42XX8_STATUSCTL_INI_WIDTH) - 1) << CS42XX8_STATUSCTL_INI_SHIFT)
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#define CS42XX8_STATUSCTL_INT_ACTIVE_HIGH (0 << CS42XX8_STATUSCTL_INI_SHIFT)
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#define CS42XX8_STATUSCTL_INT_ACTIVE_LOW (1 << CS42XX8_STATUSCTL_INI_SHIFT)
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#define CS42XX8_STATUSCTL_INT_OPEN_DRAIN (2 << CS42XX8_STATUSCTL_INI_SHIFT)
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/* Status (Address 19h)*/
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#define CS42XX8_STATUS_DAC_CLK_ERR_SHIFT 4
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#define CS42XX8_STATUS_DAC_CLK_ERR_MASK (1 << CS42XX8_STATUS_DAC_CLK_ERR_SHIFT)
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#define CS42XX8_STATUS_ADC_CLK_ERR_SHIFT 3
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#define CS42XX8_STATUS_ADC_CLK_ERR_MASK (1 << CS42XX8_STATUS_ADC_CLK_ERR_SHIFT)
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#define CS42XX8_STATUS_ADC3_OVFL_SHIFT 2
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#define CS42XX8_STATUS_ADC3_OVFL_MASK (1 << CS42XX8_STATUS_ADC3_OVFL_SHIFT)
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#define CS42XX8_STATUS_ADC2_OVFL_SHIFT 1
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#define CS42XX8_STATUS_ADC2_OVFL_MASK (1 << CS42XX8_STATUS_ADC2_OVFL_SHIFT)
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#define CS42XX8_STATUS_ADC1_OVFL_SHIFT 0
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#define CS42XX8_STATUS_ADC1_OVFL_MASK (1 << CS42XX8_STATUS_ADC1_OVFL_SHIFT)
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/* Status Mask (Address 1Ah) */
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#define CS42XX8_STATUS_DAC_CLK_ERR_M_SHIFT 4
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#define CS42XX8_STATUS_DAC_CLK_ERR_M_MASK (1 << CS42XX8_STATUS_DAC_CLK_ERR_M_SHIFT)
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#define CS42XX8_STATUS_ADC_CLK_ERR_M_SHIFT 3
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#define CS42XX8_STATUS_ADC_CLK_ERR_M_MASK (1 << CS42XX8_STATUS_ADC_CLK_ERR_M_SHIFT)
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#define CS42XX8_STATUS_ADC3_OVFL_M_SHIFT 2
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#define CS42XX8_STATUS_ADC3_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC3_OVFL_M_SHIFT)
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#define CS42XX8_STATUS_ADC2_OVFL_M_SHIFT 1
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#define CS42XX8_STATUS_ADC2_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC2_OVFL_M_SHIFT)
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#define CS42XX8_STATUS_ADC1_OVFL_M_SHIFT 0
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#define CS42XX8_STATUS_ADC1_OVFL_M_MASK (1 << CS42XX8_STATUS_ADC1_OVFL_M_SHIFT)
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/* MUTEC Pin Control (Address 1Bh) */
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#define CS42XX8_MUTEC_MCPOLARITY_SHIFT 1
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#define CS42XX8_MUTEC_MCPOLARITY_MASK (1 << CS42XX8_MUTEC_MCPOLARITY_SHIFT)
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#define CS42XX8_MUTEC_MCPOLARITY_ACTIVE_LOW (0 << CS42XX8_MUTEC_MCPOLARITY_SHIFT)
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#define CS42XX8_MUTEC_MCPOLARITY_ACTIVE_HIGH (1 << CS42XX8_MUTEC_MCPOLARITY_SHIFT)
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#define CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT 0
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#define CS42XX8_MUTEC_MUTEC_ACTIVE_MASK (1 << CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT)
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#define CS42XX8_MUTEC_MUTEC_ACTIVE (1 << CS42XX8_MUTEC_MUTEC_ACTIVE_SHIFT)
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#endif /* _CS42XX8_H */
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