mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-20 13:30:32 +07:00
786a72d791
Lots of changes as usual, so I'm trying to be brief here. Most of the
new hardware support has the respective driver changes merged through
other trees or has had it available for a while, so this is where things
come together.
We get a DT descriptions for a couple of new SoCs, all of them variants
of other chips we already support, and usually coming with a new
evaluation board:
- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices
- Qualcomm MDM9615 LTE baseband
- NXP imx6ull, the latest and smallest i.MX6 application processor variant
- Renesas RZ/G (r8a7743 and r8a7745) application processors
- Rockchip PX3, a variant of the rk3188 chip used in Android tablets
- Rockchip rk1108 single-core application processor
- ST stm32f746 Cortex-M7 based microcontroller
- TI DRA71x automotive processors
These are commercially available consumer platforms we now support:
- Motorola Droid 4 (xt894) mobile phone
- Rikomagic MK808 Android TV stick based on Rockchips rx3066
- Cloud Engines PogoPlug v3 based on OX820
- Various Broadcom based wireless devices:
- Netgear R8500 router
- Tenda AC9 router
- TP-LINK Archer C9 V1
- Luxul XAP-1510 Access point
- Turris Omnia open hardware router based on Armada 385
And a couple of new boards targeted at developers, makers
or industrial integration:
- Macnica Sodia development platform for Altera socfpga (Cyclone V)
- MicroZed board based on Xilinx Zynq FPGA platforms
- TOPEET itop/elite based on exynos4412
- WP8548 MangOH Open Hardware platform for IOT, based on
Qualcomm MDM9615
- NextThing CHIP Pro gadget
- NanoPi M1 development board
- AM571x-IDK industrial board based on TI AM5718
- i.MX6SX UDOO Neo
- Boundary Devices Nitrogen6_SOM2 (i.MX6)
- Engicam i.CoreM6
- Grinn i.MX6UL liteSOM/liteBoard
- Toradex Colibri iMX6 module
Other changes:
- added peripherals on renesas, davinci, stm32f429, uniphier, sti,
mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm,
mvebu, allwinner, broadcom, exynos, zynq
- Continued fixes for W=1 dtc warnings
- The old STiH415/416 SoC support gets removed, these never made it into
products and have served their purpose in the kernel as a template
for teh newer chips from ST
- The exynos4415 dtsi file is removed as nothing uses it.
- Intel PXA25x can now be booted using devicetree
Conflicts:
arch/arm/boot/dts/r8a*.dtsi: a node was added
the clk tree, keep both sides and watch out for git
dropping the required '};' at the end of each side.
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caqRCe1Nq6RT0RYU0m6xVyv/ox0JTNEaB+TcvD1x4pgUQNo9sSBfiXpTzOKhLhqs
zmsfpNpj8v188Iofoju3WtwN26riJ7P4QdYIaNaH4qNQgoQbMbQICDwnpSsNJY+x
MSlNrbtYqfz6vc5fqa0mtfhF6wIFxuRnTgSLi9skWZ2l/fkn4ljF3RhN1Z86TYPv
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"Lots of changes as usual, so I'm trying to be brief here. Most of the
new hardware support has the respective driver changes merged through
other trees or has had it available for a while, so this is where
things come together.
We get a DT descriptions for a couple of new SoCs, all of them
variants of other chips we already support, and usually coming with a
new evaluation board:
- Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices
- Qualcomm MDM9615 LTE baseband
- NXP imx6ull, the latest and smallest i.MX6 application processor variant
- Renesas RZ/G (r8a7743 and r8a7745) application processors
- Rockchip PX3, a variant of the rk3188 chip used in Android tablets
- Rockchip rk1108 single-core application processor
- ST stm32f746 Cortex-M7 based microcontroller
- TI DRA71x automotive processors
These are commercially available consumer platforms we now support:
- Motorola Droid 4 (xt894) mobile phone
- Rikomagic MK808 Android TV stick based on Rockchips rx3066
- Cloud Engines PogoPlug v3 based on OX820
- Various Broadcom based wireless devices:
- Netgear R8500 router
- Tenda AC9 router
- TP-LINK Archer C9 V1
- Luxul XAP-1510 Access point
- Turris Omnia open hardware router based on Armada 385
And a couple of new boards targeted at developers, makers or
industrial integration:
- Macnica Sodia development platform for Altera socfpga (Cyclone V)
- MicroZed board based on Xilinx Zynq FPGA platforms
- TOPEET itop/elite based on exynos4412
- WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615
- NextThing CHIP Pro gadget
- NanoPi M1 development board
- AM571x-IDK industrial board based on TI AM5718
- i.MX6SX UDOO Neo
- Boundary Devices Nitrogen6_SOM2 (i.MX6)
- Engicam i.CoreM6
- Grinn i.MX6UL liteSOM/liteBoard
- Toradex Colibri iMX6 module
Other changes:
- added peripherals on renesas, davinci, stm32f429, uniphier, sti,
mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm,
mvebu, allwinner, broadcom, exynos, zynq
- Continued fixes for W=1 dtc warnings
- The old STiH415/416 SoC support gets removed, these never made it
into products and have served their purpose in the kernel as a
template for teh newer chips from ST
- The exynos4415 dtsi file is removed as nothing uses it.
- Intel PXA25x can now be booted using devicetree"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits)
arm: dts: zynq: Add MicroZed board support
ARM: dts: da850: enable high speed for mmc
ARM: dts: da850: Add node for pullup/pulldown pinconf
ARM: dts: da850: enable memctrl and mstpri nodes per board
ARM: dts: da850-lcdk: Add ethernet0 alias to DT
ARM: dts: artpec: add pcie support
ARM: dts: add support for Turris Omnia
devicetree: Add vendor prefix for CZ.NIC
ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node
ARM: dts: berlin2q-marvell-dmp: fix regulators' name
ARM: dts: Add xo to sdhc clock node on qcom platforms
ARM: dts: r8a7794: Add device node for PRR
ARM: dts: r8a7793: Add device node for PRR
ARM: dts: r8a7792: Add device node for PRR
ARM: dts: r8a7791: Add device node for PRR
ARM: dts: r8a7790: Add device node for PRR
ARM: dts: r8a7779: Add device node for PRR
ARM: dts: r8a73a4: Add device node for PRR
ARM: dts: sk-rzg1e: add Ether support
ARM: dts: sk-rzg1e: initial device tree
...
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/*
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* Copyright (C) 2014 STMicroelectronics Limited.
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* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* publishhed by the Free Software Foundation.
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*/
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#include "stih407-pinctrl.dtsi"
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#include <dt-bindings/mfd/st-lpc.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/stih407-resets.h>
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#include <dt-bindings/interrupt-controller/irq-st.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gp0_reserved: rproc@40000000 {
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compatible = "shared-dma-pool";
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reg = <0x40000000 0x01000000>;
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no-map;
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status = "disabled";
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};
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gp1_reserved: rproc@41000000 {
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compatible = "shared-dma-pool";
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reg = <0x41000000 0x01000000>;
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no-map;
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status = "disabled";
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};
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audio_reserved: rproc@42000000 {
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compatible = "shared-dma-pool";
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reg = <0x42000000 0x01000000>;
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no-map;
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status = "disabled";
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};
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dmu_reserved: rproc@43000000 {
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compatible = "shared-dma-pool";
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reg = <0x43000000 0x01000000>;
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no-map;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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/* u-boot puts hpen in SBC dmem at 0xa4 offset */
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cpu-release-addr = <0x94100A4>;
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/* kHz uV */
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operating-points = <1500000 0
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1200000 0
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800000 0
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500000 0>;
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clocks = <&clk_m_a9>;
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clock-names = "cpu";
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clock-latency = <100000>;
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cpu0-supply = <&pwm_regulator>;
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st,syscfg = <&syscfg_core 0x8e0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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/* u-boot puts hpen in SBC dmem at 0xa4 offset */
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cpu-release-addr = <0x94100A4>;
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/* kHz uV */
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operating-points = <1500000 0
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1200000 0
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800000 0
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500000 0>;
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};
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};
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intc: interrupt-controller@08761000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x08761000 0x1000>, <0x08760100 0x100>;
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};
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scu@08760000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x08760000 0x1000>;
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};
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timer@08760200 {
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interrupt-parent = <&intc>;
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x08760200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&arm_periph_clk>;
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};
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l2: cache-controller {
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compatible = "arm,pl310-cache";
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reg = <0x08762000 0x1000>;
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arm,data-latency = <3 3 3>;
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arm,tag-latency = <2 2 2>;
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cache-unified;
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cache-level = <2>;
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};
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arm-pmu {
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interrupt-parent = <&intc>;
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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pwm_regulator: pwm-regulator {
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compatible = "pwm-regulator";
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pwms = <&pwm1 3 8448>;
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regulator-name = "CPU_1V0_AVS";
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regulator-min-microvolt = <784000>;
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regulator-max-microvolt = <1299000>;
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regulator-always-on;
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max-duty-cycle = <255>;
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status = "okay";
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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compatible = "simple-bus";
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restart {
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compatible = "st,stih407-restart";
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st,syscfg = <&syscfg_sbc_reg>;
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status = "okay";
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};
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powerdown: powerdown-controller {
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compatible = "st,stih407-powerdown";
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#reset-cells = <1>;
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};
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softreset: softreset-controller {
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compatible = "st,stih407-softreset";
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#reset-cells = <1>;
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};
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picophyreset: picophyreset-controller {
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compatible = "st,stih407-picophyreset";
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#reset-cells = <1>;
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};
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syscfg_sbc: sbc-syscfg@9620000 {
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compatible = "st,stih407-sbc-syscfg", "syscon";
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reg = <0x9620000 0x1000>;
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};
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syscfg_front: front-syscfg@9280000 {
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compatible = "st,stih407-front-syscfg", "syscon";
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reg = <0x9280000 0x1000>;
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};
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syscfg_rear: rear-syscfg@9290000 {
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compatible = "st,stih407-rear-syscfg", "syscon";
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reg = <0x9290000 0x1000>;
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};
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syscfg_flash: flash-syscfg@92a0000 {
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compatible = "st,stih407-flash-syscfg", "syscon";
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reg = <0x92a0000 0x1000>;
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};
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syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
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compatible = "st,stih407-sbc-reg-syscfg", "syscon";
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reg = <0x9600000 0x1000>;
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};
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syscfg_core: core-syscfg@92b0000 {
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compatible = "st,stih407-core-syscfg", "syscon";
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reg = <0x92b0000 0x1000>;
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};
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syscfg_lpm: lpm-syscfg@94b5100 {
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compatible = "st,stih407-lpm-syscfg", "syscon";
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reg = <0x94b5100 0x1000>;
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};
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irq-syscfg {
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compatible = "st,stih407-irq-syscfg";
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st,syscfg = <&syscfg_core>;
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st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
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<ST_IRQ_SYSCFG_PMU_1>;
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st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
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<ST_IRQ_SYSCFG_DISABLED>;
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};
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/* Display */
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vtg_main: sti-vtg-main@8d02800 {
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compatible = "st,vtg";
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reg = <0x8d02800 0x200>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>;
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};
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vtg_aux: sti-vtg-aux@8d00200 {
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compatible = "st,vtg";
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reg = <0x8d00200 0x100>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>;
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};
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serial@9830000 {
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compatible = "st,asc";
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reg = <0x9830000 0x2c>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_serial0>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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status = "disabled";
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};
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serial@9831000 {
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compatible = "st,asc";
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reg = <0x9831000 0x2c>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_serial1>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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status = "disabled";
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};
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serial@9832000 {
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compatible = "st,asc";
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reg = <0x9832000 0x2c>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_serial2>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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status = "disabled";
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};
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/* SBC_ASC0 - UART10 */
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sbc_serial0: serial@9530000 {
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compatible = "st,asc";
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reg = <0x9530000 0x2c>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sbc_serial0>;
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clocks = <&clk_sysin>;
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status = "disabled";
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};
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serial@9531000 {
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compatible = "st,asc";
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reg = <0x9531000 0x2c>;
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interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sbc_serial1>;
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clocks = <&clk_sysin>;
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status = "disabled";
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};
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i2c@9840000 {
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compatible = "st,comms-ssc4-i2c";
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x9840000 0x110>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0_default>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c@9841000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0x9841000 0x110>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c@9842000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0x9842000 0x110>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2_default>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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|
i2c@9843000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0x9843000 0x110>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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|
clock-frequency = <400000>;
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|
pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3_default>;
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|
#address-cells = <1>;
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#size-cells = <0>;
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|
|
status = "disabled";
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};
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|
i2c@9844000 {
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compatible = "st,comms-ssc4-i2c";
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reg = <0x9844000 0x110>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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clock-names = "ssc";
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|
clock-frequency = <400000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c4_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@9845000 {
|
|
compatible = "st,comms-ssc4-i2c";
|
|
reg = <0x9845000 0x110>;
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
|
|
clock-names = "ssc";
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c5_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
|
|
/* SSCs on SBC */
|
|
i2c@9540000 {
|
|
compatible = "st,comms-ssc4-i2c";
|
|
reg = <0x9540000 0x110>;
|
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_sysin>;
|
|
clock-names = "ssc";
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c10_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c@9541000 {
|
|
compatible = "st,comms-ssc4-i2c";
|
|
reg = <0x9541000 0x110>;
|
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_sysin>;
|
|
clock-names = "ssc";
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c11_default>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2_picophy0: phy1 {
|
|
compatible = "st,stih407-usb2-phy";
|
|
#phy-cells = <0>;
|
|
st,syscfg = <&syscfg_core 0x100 0xf4>;
|
|
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
|
|
<&picophyreset STIH407_PICOPHY2_RESET>;
|
|
reset-names = "global", "port";
|
|
};
|
|
|
|
miphy28lp_phy: miphy28lp@9b22000 {
|
|
compatible = "st,miphy28lp-phy";
|
|
st,syscfg = <&syscfg_core>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
phy_port0: port@9b22000 {
|
|
reg = <0x9b22000 0xff>,
|
|
<0x9b09000 0xff>,
|
|
<0x9b04000 0xff>;
|
|
reg-names = "sata-up",
|
|
"pcie-up",
|
|
"pipew";
|
|
|
|
st,syscfg = <0x114 0x818 0xe0 0xec>;
|
|
#phy-cells = <1>;
|
|
|
|
reset-names = "miphy-sw-rst";
|
|
resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
|
|
};
|
|
|
|
phy_port1: port@9b2a000 {
|
|
reg = <0x9b2a000 0xff>,
|
|
<0x9b19000 0xff>,
|
|
<0x9b14000 0xff>;
|
|
reg-names = "sata-up",
|
|
"pcie-up",
|
|
"pipew";
|
|
|
|
st,syscfg = <0x118 0x81c 0xe4 0xf0>;
|
|
|
|
#phy-cells = <1>;
|
|
|
|
reset-names = "miphy-sw-rst";
|
|
resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
|
|
};
|
|
|
|
phy_port2: port@8f95000 {
|
|
reg = <0x8f95000 0xff>,
|
|
<0x8f90000 0xff>;
|
|
reg-names = "pipew",
|
|
"usb3-up";
|
|
|
|
st,syscfg = <0x11c 0x820>;
|
|
|
|
#phy-cells = <1>;
|
|
|
|
reset-names = "miphy-sw-rst";
|
|
resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
|
|
};
|
|
};
|
|
|
|
spi@9840000 {
|
|
compatible = "st,comms-ssc4-spi";
|
|
reg = <0x9840000 0x110>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
|
|
clock-names = "ssc";
|
|
pinctrl-0 = <&pinctrl_spi0_default>;
|
|
pinctrl-names = "default";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@9841000 {
|
|
compatible = "st,comms-ssc4-spi";
|
|
reg = <0x9841000 0x110>;
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
|
|
clock-names = "ssc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi1_default>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@9842000 {
|
|
compatible = "st,comms-ssc4-spi";
|
|
reg = <0x9842000 0x110>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
|
|
clock-names = "ssc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi2_default>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@9843000 {
|
|
compatible = "st,comms-ssc4-spi";
|
|
reg = <0x9843000 0x110>;
|
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
|
|
clock-names = "ssc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi3_default>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@9844000 {
|
|
compatible = "st,comms-ssc4-spi";
|
|
reg = <0x9844000 0x110>;
|
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
|
|
clock-names = "ssc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi4_default>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
/* SBC SSC */
|
|
spi@9540000 {
|
|
compatible = "st,comms-ssc4-spi";
|
|
reg = <0x9540000 0x110>;
|
|
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_sysin>;
|
|
clock-names = "ssc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi10_default>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@9541000 {
|
|
compatible = "st,comms-ssc4-spi";
|
|
reg = <0x9541000 0x110>;
|
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_sysin>;
|
|
clock-names = "ssc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi11_default>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi@9542000 {
|
|
compatible = "st,comms-ssc4-spi";
|
|
reg = <0x9542000 0x110>;
|
|
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk_sysin>;
|
|
clock-names = "ssc";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_spi12_default>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc0: sdhci@09060000 {
|
|
compatible = "st,sdhci-stih407", "st,sdhci";
|
|
status = "disabled";
|
|
reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
|
|
reg-names = "mmc", "top-mmc-delay";
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
|
|
interrupt-names = "mmcirq";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_mmc0>;
|
|
clock-names = "mmc", "icn";
|
|
clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
|
|
<&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
|
|
bus-width = <8>;
|
|
};
|
|
|
|
mmc1: sdhci@09080000 {
|
|
compatible = "st,sdhci-stih407", "st,sdhci";
|
|
status = "disabled";
|
|
reg = <0x09080000 0x7ff>;
|
|
reg-names = "mmc";
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
|
|
interrupt-names = "mmcirq";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_sd1>;
|
|
clock-names = "mmc", "icn";
|
|
clocks = <&clk_s_c0_flexgen CLK_MMC_1>,
|
|
<&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
|
|
resets = <&softreset STIH407_MMC1_SOFTRESET>;
|
|
bus-width = <4>;
|
|
};
|
|
|
|
/* Watchdog and Real-Time Clock */
|
|
lpc@8787000 {
|
|
compatible = "st,stih407-lpc";
|
|
reg = <0x8787000 0x1000>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
|
|
timeout-sec = <120>;
|
|
st,syscfg = <&syscfg_core>;
|
|
st,lpc-mode = <ST_LPC_MODE_WDT>;
|
|
};
|
|
|
|
lpc@8788000 {
|
|
compatible = "st,stih407-lpc";
|
|
reg = <0x8788000 0x1000>;
|
|
interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
|
|
st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
|
|
};
|
|
|
|
sata0: sata@9b20000 {
|
|
compatible = "st,ahci";
|
|
reg = <0x9b20000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
|
|
interrupt-names = "hostc";
|
|
|
|
phys = <&phy_port0 PHY_TYPE_SATA>;
|
|
phy-names = "ahci_phy";
|
|
|
|
resets = <&powerdown STIH407_SATA0_POWERDOWN>,
|
|
<&softreset STIH407_SATA0_SOFTRESET>,
|
|
<&softreset STIH407_SATA0_PWR_SOFTRESET>;
|
|
reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
|
|
|
|
clock-names = "ahci_clk";
|
|
clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
|
|
|
|
ports-implemented = <0x1>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
sata1: sata@9b28000 {
|
|
compatible = "st,ahci";
|
|
reg = <0x9b28000 0x1000>;
|
|
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
|
|
interrupt-names = "hostc";
|
|
|
|
phys = <&phy_port1 PHY_TYPE_SATA>;
|
|
phy-names = "ahci_phy";
|
|
|
|
resets = <&powerdown STIH407_SATA1_POWERDOWN>,
|
|
<&softreset STIH407_SATA1_SOFTRESET>,
|
|
<&softreset STIH407_SATA1_PWR_SOFTRESET>;
|
|
reset-names = "pwr-dwn",
|
|
"sw-rst",
|
|
"pwr-rst";
|
|
|
|
clock-names = "ahci_clk";
|
|
clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
|
|
|
|
ports-implemented = <0x1>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
|
|
st_dwc3: dwc3@8f94000 {
|
|
compatible = "st,stih407-dwc3";
|
|
reg = <0x08f94000 0x1000>, <0x110 0x4>;
|
|
reg-names = "reg-glue", "syscfg-reg";
|
|
st,syscfg = <&syscfg_core>;
|
|
resets = <&powerdown STIH407_USB3_POWERDOWN>,
|
|
<&softreset STIH407_MIPHY2_SOFTRESET>;
|
|
reset-names = "powerdown", "softreset";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb3>;
|
|
ranges;
|
|
|
|
status = "disabled";
|
|
|
|
dwc3: dwc3@9900000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x09900000 0x100000>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
|
|
dr_mode = "host";
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
phys = <&usb2_picophy0>,
|
|
<&phy_port2 PHY_TYPE_USB3>;
|
|
};
|
|
};
|
|
|
|
/* COMMS PWM Module */
|
|
pwm0: pwm@9810000 {
|
|
compatible = "st,sti-pwm";
|
|
#pwm-cells = <2>;
|
|
reg = <0x9810000 0x68>;
|
|
interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
|
|
clock-names = "pwm";
|
|
clocks = <&clk_sysin>;
|
|
st,pwm-num-chan = <1>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
/* SBC PWM Module */
|
|
pwm1: pwm@9510000 {
|
|
compatible = "st,sti-pwm";
|
|
#pwm-cells = <2>;
|
|
reg = <0x9510000 0x68>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm1_chan0_default
|
|
&pinctrl_pwm1_chan1_default
|
|
&pinctrl_pwm1_chan2_default
|
|
&pinctrl_pwm1_chan3_default>;
|
|
clock-names = "pwm";
|
|
clocks = <&clk_sysin>;
|
|
st,pwm-num-chan = <4>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
rng10: rng@08a89000 {
|
|
compatible = "st,rng";
|
|
reg = <0x08a89000 0x1000>;
|
|
clocks = <&clk_sysin>;
|
|
status = "okay";
|
|
};
|
|
|
|
rng11: rng@08a8a000 {
|
|
compatible = "st,rng";
|
|
reg = <0x08a8a000 0x1000>;
|
|
clocks = <&clk_sysin>;
|
|
status = "okay";
|
|
};
|
|
|
|
ethernet0: dwmac@9630000 {
|
|
device_type = "network";
|
|
status = "disabled";
|
|
compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
|
|
reg = <0x9630000 0x8000>, <0x80 0x4>;
|
|
reg-names = "stmmaceth", "sti-ethconf";
|
|
|
|
st,syscon = <&syscfg_sbc_reg 0x80>;
|
|
st,gmac_en;
|
|
resets = <&softreset STIH407_ETH1_SOFTRESET>;
|
|
reset-names = "stmmaceth";
|
|
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
|
|
<GIC_SPI 99 IRQ_TYPE_NONE>;
|
|
interrupt-names = "macirq", "eth_wake_irq";
|
|
|
|
/* DMA Bus Mode */
|
|
snps,pbl = <8>;
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_rgmii1>;
|
|
|
|
clock-names = "stmmaceth", "sti-ethclk";
|
|
clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
|
|
<&clk_s_c0_flexgen CLK_ETH_PHY>;
|
|
};
|
|
|
|
cec: sti-cec@094a087c {
|
|
compatible = "st,stih-cec";
|
|
reg = <0x94a087c 0x64>;
|
|
clocks = <&clk_sysin>;
|
|
clock-names = "cec-clk";
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_NONE>;
|
|
interrupt-names = "cec-irq";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_cec0_default>;
|
|
resets = <&softreset STIH407_LPM_SOFTRESET>;
|
|
};
|
|
|
|
rng10: rng@08a89000 {
|
|
compatible = "st,rng";
|
|
reg = <0x08a89000 0x1000>;
|
|
clocks = <&clk_sysin>;
|
|
status = "okay";
|
|
};
|
|
|
|
rng11: rng@08a8a000 {
|
|
compatible = "st,rng";
|
|
reg = <0x08a8a000 0x1000>;
|
|
clocks = <&clk_sysin>;
|
|
status = "okay";
|
|
};
|
|
|
|
mailbox0: mailbox@8f00000 {
|
|
compatible = "st,stih407-mailbox";
|
|
reg = <0x8f00000 0x1000>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
|
|
#mbox-cells = <2>;
|
|
mbox-name = "a9";
|
|
status = "okay";
|
|
};
|
|
|
|
mailbox1: mailbox@8f01000 {
|
|
compatible = "st,stih407-mailbox";
|
|
reg = <0x8f01000 0x1000>;
|
|
#mbox-cells = <2>;
|
|
mbox-name = "st231_gp_1";
|
|
status = "okay";
|
|
};
|
|
|
|
mailbox2: mailbox@8f02000 {
|
|
compatible = "st,stih407-mailbox";
|
|
reg = <0x8f02000 0x1000>;
|
|
#mbox-cells = <2>;
|
|
mbox-name = "st231_gp_0";
|
|
status = "okay";
|
|
};
|
|
|
|
mailbox3: mailbox@8f03000 {
|
|
compatible = "st,stih407-mailbox";
|
|
reg = <0x8f03000 0x1000>;
|
|
#mbox-cells = <2>;
|
|
mbox-name = "st231_audio_video";
|
|
status = "okay";
|
|
};
|
|
|
|
st231_gp0: remote-processor {
|
|
compatible = "st,st231-rproc";
|
|
memory-region = <&gp0_reserved>;
|
|
resets = <&softreset STIH407_ST231_GP0_SOFTRESET>;
|
|
reset-names = "sw_reset";
|
|
clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>;
|
|
clock-frequency = <600000000>;
|
|
st,syscfg = <&syscfg_core 0x22c>;
|
|
};
|
|
|
|
|
|
st231_gp1: remote-processor {
|
|
compatible = "st,st231-rproc";
|
|
memory-region = <&gp1_reserved>;
|
|
resets = <&softreset STIH407_ST231_GP1_SOFTRESET>;
|
|
reset-names = "sw_reset";
|
|
clocks = <&clk_s_c0_flexgen CLK_ST231_GP_1>;
|
|
clock-frequency = <600000000>;
|
|
st,syscfg = <&syscfg_core 0x220>;
|
|
};
|
|
|
|
st231_audio: remote-processor {
|
|
compatible = "st,st231-rproc";
|
|
memory-region = <&audio_reserved>;
|
|
resets = <&softreset STIH407_ST231_AUD_SOFTRESET>;
|
|
reset-names = "sw_reset";
|
|
clocks = <&clk_s_c0_flexgen CLK_ST231_AUD_0>;
|
|
clock-frequency = <600000000>;
|
|
st,syscfg = <&syscfg_core 0x228>;
|
|
};
|
|
|
|
st231_dmu: remote-processor {
|
|
compatible = "st,st231-rproc";
|
|
memory-region = <&dmu_reserved>;
|
|
resets = <&softreset STIH407_ST231_DMU_SOFTRESET>;
|
|
reset-names = "sw_reset";
|
|
clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>;
|
|
clock-frequency = <600000000>;
|
|
st,syscfg = <&syscfg_core 0x224>;
|
|
};
|
|
|
|
/* fdma audio */
|
|
fdma0: dma-controller@8e20000 {
|
|
compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
|
|
reg = <0x8e20000 0x8000>,
|
|
<0x8e30000 0x3000>,
|
|
<0x8e37000 0x1000>,
|
|
<0x8e38000 0x8000>;
|
|
reg-names = "slimcore", "dmem", "peripherals", "imem";
|
|
clocks = <&clk_s_c0_flexgen CLK_FDMA>,
|
|
<&clk_s_c0_flexgen CLK_EXT2F_A9>,
|
|
<&clk_s_c0_flexgen CLK_EXT2F_A9>,
|
|
<&clk_s_c0_flexgen CLK_EXT2F_A9>;
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
|
|
dma-channels = <16>;
|
|
#dma-cells = <3>;
|
|
};
|
|
|
|
/* fdma app */
|
|
fdma1: dma-controller@8e40000 {
|
|
compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc";
|
|
reg = <0x8e40000 0x8000>,
|
|
<0x8e50000 0x3000>,
|
|
<0x8e57000 0x1000>,
|
|
<0x8e58000 0x8000>;
|
|
reg-names = "slimcore", "dmem", "peripherals", "imem";
|
|
clocks = <&clk_s_c0_flexgen CLK_FDMA>,
|
|
<&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
|
|
<&clk_s_c0_flexgen CLK_TX_ICN_DMU>,
|
|
<&clk_s_c0_flexgen CLK_EXT2F_A9>;
|
|
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>;
|
|
dma-channels = <16>;
|
|
#dma-cells = <3>;
|
|
};
|
|
|
|
/* fdma free running */
|
|
fdma2: dma-controller@8e60000 {
|
|
compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc";
|
|
reg = <0x8e60000 0x8000>,
|
|
<0x8e70000 0x3000>,
|
|
<0x8e77000 0x1000>,
|
|
<0x8e78000 0x8000>;
|
|
reg-names = "slimcore", "dmem", "peripherals", "imem";
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_NONE>;
|
|
dma-channels = <16>;
|
|
#dma-cells = <3>;
|
|
clocks = <&clk_s_c0_flexgen CLK_FDMA>,
|
|
<&clk_s_c0_flexgen CLK_EXT2F_A9>,
|
|
<&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
|
|
<&clk_s_c0_flexgen CLK_EXT2F_A9>;
|
|
};
|
|
|
|
sti_sasg_codec: sti-sasg-codec {
|
|
compatible = "st,stih407-sas-codec";
|
|
#sound-dai-cells = <1>;
|
|
status = "disabled";
|
|
st,syscfg = <&syscfg_core>;
|
|
};
|
|
|
|
sti_uni_player0: sti-uni-player@8d80000 {
|
|
compatible = "st,stih407-uni-player-hdmi";
|
|
#sound-dai-cells = <0>;
|
|
st,syscfg = <&syscfg_core>;
|
|
clocks = <&clk_s_d0_flexgen CLK_PCM_0>;
|
|
assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>;
|
|
assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>;
|
|
assigned-clock-rates = <50000000>;
|
|
reg = <0x8d80000 0x158>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_NONE>;
|
|
dmas = <&fdma0 2 0 1>;
|
|
dma-names = "tx";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
sti_uni_player1: sti-uni-player@8d81000 {
|
|
compatible = "st,stih407-uni-player-pcm-out";
|
|
#sound-dai-cells = <0>;
|
|
st,syscfg = <&syscfg_core>;
|
|
clocks = <&clk_s_d0_flexgen CLK_PCM_1>;
|
|
assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>;
|
|
assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>;
|
|
assigned-clock-rates = <50000000>;
|
|
reg = <0x8d81000 0x158>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
|
|
dmas = <&fdma0 3 0 1>;
|
|
dma-names = "tx";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
sti_uni_player2: sti-uni-player@8d82000 {
|
|
compatible = "st,stih407-uni-player-dac";
|
|
#sound-dai-cells = <0>;
|
|
st,syscfg = <&syscfg_core>;
|
|
clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
|
|
assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>;
|
|
assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>;
|
|
assigned-clock-rates = <50000000>;
|
|
reg = <0x8d82000 0x158>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
|
|
dmas = <&fdma0 4 0 1>;
|
|
dma-names = "tx";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
sti_uni_player3: sti-uni-player@8d85000 {
|
|
compatible = "st,stih407-uni-player-spdif";
|
|
#sound-dai-cells = <0>;
|
|
st,syscfg = <&syscfg_core>;
|
|
clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
|
|
assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>;
|
|
assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>;
|
|
assigned-clock-rates = <50000000>;
|
|
reg = <0x8d85000 0x158>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
|
|
dmas = <&fdma0 7 0 1>;
|
|
dma-names = "tx";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
sti_uni_reader0: sti-uni-reader@8d83000 {
|
|
compatible = "st,stih407-uni-reader-pcm_in";
|
|
#sound-dai-cells = <0>;
|
|
st,syscfg = <&syscfg_core>;
|
|
reg = <0x8d83000 0x158>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_NONE>;
|
|
dmas = <&fdma0 5 0 1>;
|
|
dma-names = "rx";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
sti_uni_reader1: sti-uni-reader@8d84000 {
|
|
compatible = "st,stih407-uni-reader-hdmi";
|
|
#sound-dai-cells = <0>;
|
|
st,syscfg = <&syscfg_core>;
|
|
reg = <0x8d84000 0x158>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
|
|
dmas = <&fdma0 6 0 1>;
|
|
dma-names = "rx";
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|