mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 05:16:53 +07:00
31849483f1
Corrected type of flash in output (OneNAND => NOR). Removed whitespace after newline in output. Removed double whitespace in output. Signed-off-by: Thomas Weber <weber@corscience.de> Signed-off-by: Tony Lindgren <tony@atomide.com>
273 lines
6.8 KiB
C
273 lines
6.8 KiB
C
/*
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* board-sdp-flash.c
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* Modified from mach-omap2/board-3430sdp-flash.c
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*
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* Copyright (C) 2009 Nokia Corporation
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* Copyright (C) 2009 Texas Instruments
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*
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* Vimal Singh <vimalsingh@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/physmap.h>
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#include <linux/io.h>
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#include <plat/gpmc.h>
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#include <plat/nand.h>
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#include <plat/onenand.h>
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#include <plat/tc.h>
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#include <mach/board-sdp.h>
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#define REG_FPGA_REV 0x10
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#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
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#define MAX_SUPPORTED_GPMC_CONFIG 3
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#define DEBUG_BASE 0x08000000 /* debug board */
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#define PDC_NOR 1
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#define PDC_NAND 2
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#define PDC_ONENAND 3
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#define DBG_MPDB 4
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/* various memory sizes */
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#define FLASH_SIZE_SDPV1 SZ_64M /* NOR flash (64 Meg aligned) */
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#define FLASH_SIZE_SDPV2 SZ_128M /* NOR flash (256 Meg aligned) */
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/*
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* SDP3430 V2 Board CS organization
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* Different from SDP3430 V1. Now 4 switches used to specify CS
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*
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* See also the Switch S8 settings in the comments.
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*
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* REVISIT: Add support for 2430 SDP
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*/
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static const unsigned char chip_sel_sdp[][GPMC_CS_NUM] = {
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{PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
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{PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
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{PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
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};
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static struct physmap_flash_data sdp_nor_data = {
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.width = 2,
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};
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static struct resource sdp_nor_resource = {
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device sdp_nor_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &sdp_nor_data,
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},
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.num_resources = 1,
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.resource = &sdp_nor_resource,
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};
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static void
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__init board_nor_init(struct flash_partitions sdp_nor_parts, u8 cs)
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{
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int err;
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sdp_nor_data.parts = sdp_nor_parts.parts;
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sdp_nor_data.nr_parts = sdp_nor_parts.nr_parts;
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/* Configure start address and size of NOR device */
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if (omap_rev() >= OMAP3430_REV_ES1_0) {
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err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1,
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(unsigned long *)&sdp_nor_resource.start);
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sdp_nor_resource.end = sdp_nor_resource.start
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+ FLASH_SIZE_SDPV2 - 1;
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} else {
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err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1,
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(unsigned long *)&sdp_nor_resource.start);
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sdp_nor_resource.end = sdp_nor_resource.start
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+ FLASH_SIZE_SDPV1 - 1;
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}
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if (err < 0) {
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printk(KERN_ERR "NOR: Can't request GPMC CS\n");
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return;
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}
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if (platform_device_register(&sdp_nor_device) < 0)
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printk(KERN_ERR "Unable to register NOR device\n");
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}
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#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
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defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
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static struct omap_onenand_platform_data board_onenand_data = {
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.dma_channel = -1, /* disable DMA in OMAP OneNAND driver */
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};
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static void
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__init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs)
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{
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board_onenand_data.cs = cs;
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board_onenand_data.parts = sdp_onenand_parts.parts;
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board_onenand_data.nr_parts = sdp_onenand_parts.nr_parts;
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gpmc_onenand_init(&board_onenand_data);
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}
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#else
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static void
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__init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs)
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{
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}
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#endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */
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#if defined(CONFIG_MTD_NAND_OMAP2) || \
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defined(CONFIG_MTD_NAND_OMAP2_MODULE)
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/* Note that all values in this struct are in nanoseconds */
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static struct gpmc_timings nand_timings = {
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.sync_clk = 0,
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.cs_on = 0,
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.cs_rd_off = 36,
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.cs_wr_off = 36,
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.adv_on = 6,
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.adv_rd_off = 24,
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.adv_wr_off = 36,
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.we_off = 30,
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.oe_off = 48,
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.access = 54,
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.rd_cycle = 72,
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.wr_cycle = 72,
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.wr_access = 30,
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.wr_data_mux_bus = 0,
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};
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static struct omap_nand_platform_data sdp_nand_data = {
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.nand_setup = NULL,
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.gpmc_t = &nand_timings,
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.dma_channel = -1, /* disable DMA in OMAP NAND driver */
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.dev_ready = NULL,
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.devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */
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};
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static void
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__init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs)
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{
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sdp_nand_data.cs = cs;
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sdp_nand_data.parts = sdp_nand_parts.parts;
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sdp_nand_data.nr_parts = sdp_nand_parts.nr_parts;
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sdp_nand_data.gpmc_cs_baseaddr = (void *)(OMAP34XX_GPMC_VIRT +
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GPMC_CS0_BASE +
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cs * GPMC_CS_SIZE);
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sdp_nand_data.gpmc_baseaddr = (void *) (OMAP34XX_GPMC_VIRT);
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gpmc_nand_init(&sdp_nand_data);
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}
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#else
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static void
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__init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs)
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{
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}
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#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
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/**
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* get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get
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* the various cs values.
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*/
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static u8 get_gpmc0_type(void)
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{
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u8 cs = 0;
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void __iomem *fpga_map_addr;
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fpga_map_addr = ioremap(DEBUG_BASE, 4096);
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if (!fpga_map_addr)
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return -ENOMEM;
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if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV)))
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/* we dont have an DEBUG FPGA??? */
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/* Depend on #defines!! default to strata boot return param */
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goto unmap;
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/* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
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cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
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/* ES2.0 SDP's onwards 4 dip switches are provided for CS */
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if (omap_rev() >= OMAP3430_REV_ES1_0)
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/* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */
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cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) |
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((cs & 2) << 1) | ((cs & 1) << 3);
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else
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/* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */
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cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2);
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unmap:
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iounmap(fpga_map_addr);
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return cs;
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}
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/**
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* sdp3430_flash_init - Identify devices connected to GPMC and register.
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*
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* @return - void.
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*/
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void __init sdp_flash_init(struct flash_partitions sdp_partition_info[])
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{
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u8 cs = 0;
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u8 norcs = GPMC_CS_NUM + 1;
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u8 nandcs = GPMC_CS_NUM + 1;
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u8 onenandcs = GPMC_CS_NUM + 1;
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u8 idx;
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unsigned char *config_sel = NULL;
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/* REVISIT: Is this return correct idx for 2430 SDP?
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* for which cs configuration matches for 2430 SDP?
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*/
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idx = get_gpmc0_type();
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if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
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printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs);
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return;
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}
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config_sel = (unsigned char *)(chip_sel_sdp[idx]);
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while (cs < GPMC_CS_NUM) {
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switch (config_sel[cs]) {
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case PDC_NOR:
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if (norcs > GPMC_CS_NUM)
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norcs = cs;
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break;
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case PDC_NAND:
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if (nandcs > GPMC_CS_NUM)
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nandcs = cs;
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break;
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case PDC_ONENAND:
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if (onenandcs > GPMC_CS_NUM)
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onenandcs = cs;
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break;
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};
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cs++;
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}
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if (norcs > GPMC_CS_NUM)
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printk(KERN_INFO "NOR: Unable to find configuration "
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"in GPMC\n");
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else
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board_nor_init(sdp_partition_info[0], norcs);
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if (onenandcs > GPMC_CS_NUM)
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printk(KERN_INFO "OneNAND: Unable to find configuration "
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"in GPMC\n");
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else
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board_onenand_init(sdp_partition_info[1], onenandcs);
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if (nandcs > GPMC_CS_NUM)
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printk(KERN_INFO "NAND: Unable to find configuration "
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"in GPMC\n");
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else
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board_nand_init(sdp_partition_info[2], nandcs);
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}
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