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Based on 2 normalized pattern(s): driver is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version the [carillo] [ranch] [video] [subsystem] driver is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this driver if not write to the free software foundation inc 51 franklin st fifth floor boston ma 02110 1301 usa driver is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version the [vermilion] [range] [fb] driver is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this driver if not write to the free software foundation inc 51 franklin st fifth floor boston ma 02110 1301 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 4 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190520071858.916314029@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
196 lines
4.0 KiB
C
196 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) Intel Corp. 2007.
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* All Rights Reserved.
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*
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* Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
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* develop this driver.
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*
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* This file is part of the Carillo Ranch video subsystem driver.
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*
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* Authors:
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* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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* Alan Hourihane <alanh-at-tungstengraphics-dot-com>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/errno.h>
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#include <linux/fb.h>
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#include "vermilion.h"
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/* The PLL Clock register sits on Host bridge */
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#define CRVML_DEVICE_MCH 0x5001
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#define CRVML_REG_MCHBAR 0x44
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#define CRVML_REG_MCHEN 0x54
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#define CRVML_MCHEN_BIT (1 << 28)
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#define CRVML_MCHMAP_SIZE 4096
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#define CRVML_REG_CLOCK 0xc3c
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#define CRVML_CLOCK_SHIFT 8
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#define CRVML_CLOCK_MASK 0x00000f00
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static struct pci_dev *mch_dev;
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static u32 mch_bar;
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static void __iomem *mch_regs_base;
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static u32 saved_clock;
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static const unsigned crvml_clocks[] = {
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6750,
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13500,
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27000,
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29700,
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37125,
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54000,
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59400,
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74250,
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120000
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/*
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* There are more clocks, but they are disabled on the CR board.
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*/
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};
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static const u32 crvml_clock_bits[] = {
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0x0a,
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0x09,
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0x08,
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0x07,
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0x06,
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0x05,
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0x04,
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0x03,
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0x0b
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};
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static const unsigned crvml_num_clocks = ARRAY_SIZE(crvml_clocks);
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static int crvml_sys_restore(struct vml_sys *sys)
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{
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void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
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iowrite32(saved_clock, clock_reg);
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ioread32(clock_reg);
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return 0;
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}
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static int crvml_sys_save(struct vml_sys *sys)
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{
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void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
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saved_clock = ioread32(clock_reg);
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return 0;
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}
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static int crvml_nearest_index(const struct vml_sys *sys, int clock)
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{
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int i;
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int cur_index = 0;
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int cur_diff;
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int diff;
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cur_diff = clock - crvml_clocks[0];
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cur_diff = (cur_diff < 0) ? -cur_diff : cur_diff;
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for (i = 1; i < crvml_num_clocks; ++i) {
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diff = clock - crvml_clocks[i];
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diff = (diff < 0) ? -diff : diff;
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if (diff < cur_diff) {
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cur_index = i;
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cur_diff = diff;
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}
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}
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return cur_index;
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}
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static int crvml_nearest_clock(const struct vml_sys *sys, int clock)
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{
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return crvml_clocks[crvml_nearest_index(sys, clock)];
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}
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static int crvml_set_clock(struct vml_sys *sys, int clock)
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{
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void __iomem *clock_reg = mch_regs_base + CRVML_REG_CLOCK;
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int index;
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u32 clock_val;
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index = crvml_nearest_index(sys, clock);
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if (crvml_clocks[index] != clock)
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return -EINVAL;
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clock_val = ioread32(clock_reg) & ~CRVML_CLOCK_MASK;
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clock_val = crvml_clock_bits[index] << CRVML_CLOCK_SHIFT;
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iowrite32(clock_val, clock_reg);
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ioread32(clock_reg);
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return 0;
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}
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static struct vml_sys cr_pll_ops = {
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.name = "Carillo Ranch",
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.save = crvml_sys_save,
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.restore = crvml_sys_restore,
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.set_clock = crvml_set_clock,
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.nearest_clock = crvml_nearest_clock,
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};
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static int __init cr_pll_init(void)
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{
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int err;
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u32 dev_en;
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mch_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
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CRVML_DEVICE_MCH, NULL);
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if (!mch_dev) {
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printk(KERN_ERR
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"Could not find Carillo Ranch MCH device.\n");
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return -ENODEV;
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}
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pci_read_config_dword(mch_dev, CRVML_REG_MCHEN, &dev_en);
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if (!(dev_en & CRVML_MCHEN_BIT)) {
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printk(KERN_ERR
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"Carillo Ranch MCH device was not enabled.\n");
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pci_dev_put(mch_dev);
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return -ENODEV;
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}
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pci_read_config_dword(mch_dev, CRVML_REG_MCHBAR,
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&mch_bar);
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mch_regs_base =
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ioremap_nocache(mch_bar, CRVML_MCHMAP_SIZE);
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if (!mch_regs_base) {
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printk(KERN_ERR
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"Carillo Ranch MCH device was not enabled.\n");
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pci_dev_put(mch_dev);
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return -ENODEV;
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}
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err = vmlfb_register_subsys(&cr_pll_ops);
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if (err) {
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printk(KERN_ERR
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"Carillo Ranch failed to initialize vml_sys.\n");
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iounmap(mch_regs_base);
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pci_dev_put(mch_dev);
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return err;
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}
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return 0;
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}
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static void __exit cr_pll_exit(void)
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{
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vmlfb_unregister_subsys(&cr_pll_ops);
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iounmap(mch_regs_base);
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pci_dev_put(mch_dev);
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}
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module_init(cr_pll_init);
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module_exit(cr_pll_exit);
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MODULE_AUTHOR("Tungsten Graphics Inc.");
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MODULE_DESCRIPTION("Carillo Ranch PLL Driver");
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MODULE_LICENSE("GPL");
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