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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
70523e639b
The 3.xx and 4.xx synopsys gmacs have a very similar PCS embedded module and they share almost the same registers: for example: AN_Control, AN_Status, AN_Advertisement, AN_Link_Partner_Ability, AN_Expansion, TBI_Extended_Status. Just the RGMII/SMII Control/Status register differs. So This patch aims to reorganize and enhance the PCS support. It removes the existent support from the dwmac1000/dwmac4_core.c moving basic PCS functions inside a new file called: stmmac_pcs.h. The patch also reviews the available APIs to be better shared among different hardware and easily enhanced to support new features. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
260 lines
8.0 KiB
C
260 lines
8.0 KiB
C
/*
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* DWMAC4 Header file.
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*
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* Copyright (C) 2015 STMicroelectronics Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* Author: Alexandre Torgue <alexandre.torgue@st.com>
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*/
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#ifndef __DWMAC4_H__
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#define __DWMAC4_H__
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#include "common.h"
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/* MAC registers */
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#define GMAC_CONFIG 0x00000000
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#define GMAC_PACKET_FILTER 0x00000008
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#define GMAC_HASH_TAB_0_31 0x00000010
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#define GMAC_HASH_TAB_32_63 0x00000014
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#define GMAC_RX_FLOW_CTRL 0x00000090
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#define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4)
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#define GMAC_INT_STATUS 0x000000b0
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#define GMAC_INT_EN 0x000000b4
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#define GMAC_PCS_BASE 0x000000e0
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#define GMAC_PHYIF_CONTROL_STATUS 0x000000f8
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#define GMAC_PMT 0x000000c0
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#define GMAC_VERSION 0x00000110
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#define GMAC_DEBUG 0x00000114
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#define GMAC_HW_FEATURE0 0x0000011c
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#define GMAC_HW_FEATURE1 0x00000120
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#define GMAC_HW_FEATURE2 0x00000124
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#define GMAC_MDIO_ADDR 0x00000200
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#define GMAC_MDIO_DATA 0x00000204
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#define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8)
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#define GMAC_ADDR_LOW(reg) (0x304 + reg * 8)
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/* MAC Packet Filtering */
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#define GMAC_PACKET_FILTER_PR BIT(0)
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#define GMAC_PACKET_FILTER_HMC BIT(2)
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#define GMAC_PACKET_FILTER_PM BIT(4)
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#define GMAC_MAX_PERFECT_ADDRESSES 128
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/* MAC Flow Control RX */
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#define GMAC_RX_FLOW_CTRL_RFE BIT(0)
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/* MAC Flow Control TX */
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#define GMAC_TX_FLOW_CTRL_TFE BIT(1)
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#define GMAC_TX_FLOW_CTRL_PT_SHIFT 16
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/* MAC Interrupt bitmap*/
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#define GMAC_INT_PMT_EN BIT(4)
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#define GMAC_INT_LPI_EN BIT(5)
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enum dwmac4_irq_status {
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time_stamp_irq = 0x00001000,
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mmc_rx_csum_offload_irq = 0x00000800,
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mmc_tx_irq = 0x00000400,
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mmc_rx_irq = 0x00000200,
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mmc_irq = 0x00000100,
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pmt_irq = 0x00000010,
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};
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/* MAC PMT bitmap */
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enum power_event {
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pointer_reset = 0x80000000,
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global_unicast = 0x00000200,
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wake_up_rx_frame = 0x00000040,
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magic_frame = 0x00000020,
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wake_up_frame_en = 0x00000004,
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magic_pkt_en = 0x00000002,
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power_down = 0x00000001,
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};
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/* MAC Debug bitmap */
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#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
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#define GMAC_DEBUG_TFCSTS_SHIFT 17
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#define GMAC_DEBUG_TFCSTS_IDLE 0
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#define GMAC_DEBUG_TFCSTS_WAIT 1
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#define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
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#define GMAC_DEBUG_TFCSTS_XFER 3
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#define GMAC_DEBUG_TPESTS BIT(16)
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#define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
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#define GMAC_DEBUG_RFCFCSTS_SHIFT 1
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#define GMAC_DEBUG_RPESTS BIT(0)
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/* MAC config */
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#define GMAC_CONFIG_IPC BIT(27)
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#define GMAC_CONFIG_2K BIT(22)
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#define GMAC_CONFIG_ACS BIT(20)
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#define GMAC_CONFIG_BE BIT(18)
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#define GMAC_CONFIG_JD BIT(17)
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#define GMAC_CONFIG_JE BIT(16)
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#define GMAC_CONFIG_PS BIT(15)
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#define GMAC_CONFIG_FES BIT(14)
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#define GMAC_CONFIG_DM BIT(13)
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#define GMAC_CONFIG_DCRS BIT(9)
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#define GMAC_CONFIG_TE BIT(1)
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#define GMAC_CONFIG_RE BIT(0)
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/* MAC HW features0 bitmap */
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#define GMAC_HW_FEAT_ADDMAC BIT(18)
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#define GMAC_HW_FEAT_RXCOESEL BIT(16)
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#define GMAC_HW_FEAT_TXCOSEL BIT(14)
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#define GMAC_HW_FEAT_EEESEL BIT(13)
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#define GMAC_HW_FEAT_TSSEL BIT(12)
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#define GMAC_HW_FEAT_MMCSEL BIT(8)
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#define GMAC_HW_FEAT_MGKSEL BIT(7)
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#define GMAC_HW_FEAT_RWKSEL BIT(6)
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#define GMAC_HW_FEAT_SMASEL BIT(5)
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#define GMAC_HW_FEAT_VLHASH BIT(4)
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#define GMAC_HW_FEAT_PCSSEL BIT(3)
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#define GMAC_HW_FEAT_HDSEL BIT(2)
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#define GMAC_HW_FEAT_GMIISEL BIT(1)
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#define GMAC_HW_FEAT_MIISEL BIT(0)
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/* MAC HW features1 bitmap */
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#define GMAC_HW_FEAT_AVSEL BIT(20)
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#define GMAC_HW_TSOEN BIT(18)
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/* MAC HW features2 bitmap */
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#define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18)
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#define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12)
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/* MAC HW ADDR regs */
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#define GMAC_HI_DCS GENMASK(18, 16)
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#define GMAC_HI_DCS_SHIFT 16
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#define GMAC_HI_REG_AE BIT(31)
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/* MTL registers */
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#define MTL_INT_STATUS 0x00000c20
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#define MTL_INT_Q0 BIT(0)
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#define MTL_CHAN_BASE_ADDR 0x00000d00
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#define MTL_CHAN_BASE_OFFSET 0x40
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#define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \
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(x * MTL_CHAN_BASE_OFFSET))
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#define MTL_CHAN_TX_OP_MODE(x) MTL_CHANX_BASE_ADDR(x)
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#define MTL_CHAN_TX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x8)
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#define MTL_CHAN_INT_CTRL(x) (MTL_CHANX_BASE_ADDR(x) + 0x2c)
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#define MTL_CHAN_RX_OP_MODE(x) (MTL_CHANX_BASE_ADDR(x) + 0x30)
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#define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38)
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#define MTL_OP_MODE_RSF BIT(5)
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#define MTL_OP_MODE_TSF BIT(1)
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#define MTL_OP_MODE_TTC_MASK 0x70
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#define MTL_OP_MODE_TTC_SHIFT 4
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#define MTL_OP_MODE_TTC_32 0
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#define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT)
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#define MTL_OP_MODE_RTC_MASK 0x18
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#define MTL_OP_MODE_RTC_SHIFT 3
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#define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT)
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#define MTL_OP_MODE_RTC_64 0
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#define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT)
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#define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT)
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/* MTL debug */
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#define MTL_DEBUG_TXSTSFSTS BIT(5)
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#define MTL_DEBUG_TXFSTS BIT(4)
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#define MTL_DEBUG_TWCSTS BIT(3)
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/* MTL debug: Tx FIFO Read Controller Status */
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#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
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#define MTL_DEBUG_TRCSTS_SHIFT 1
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#define MTL_DEBUG_TRCSTS_IDLE 0
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#define MTL_DEBUG_TRCSTS_READ 1
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#define MTL_DEBUG_TRCSTS_TXW 2
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#define MTL_DEBUG_TRCSTS_WRITE 3
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#define MTL_DEBUG_TXPAUSED BIT(0)
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/* MAC debug: GMII or MII Transmit Protocol Engine Status */
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#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
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#define MTL_DEBUG_RXFSTS_SHIFT 4
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#define MTL_DEBUG_RXFSTS_EMPTY 0
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#define MTL_DEBUG_RXFSTS_BT 1
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#define MTL_DEBUG_RXFSTS_AT 2
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#define MTL_DEBUG_RXFSTS_FULL 3
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#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
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#define MTL_DEBUG_RRCSTS_SHIFT 1
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#define MTL_DEBUG_RRCSTS_IDLE 0
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#define MTL_DEBUG_RRCSTS_RDATA 1
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#define MTL_DEBUG_RRCSTS_RSTAT 2
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#define MTL_DEBUG_RRCSTS_FLUSH 3
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#define MTL_DEBUG_RWCSTS BIT(0)
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/* MTL interrupt */
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#define MTL_RX_OVERFLOW_INT_EN BIT(24)
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#define MTL_RX_OVERFLOW_INT BIT(16)
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/* Default operating mode of the MAC */
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#define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | GMAC_CONFIG_ACS | \
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GMAC_CONFIG_BE | GMAC_CONFIG_DCRS)
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/* To dump the core regs excluding the Address Registers */
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#define GMAC_REG_NUM 132
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/* MTL debug */
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#define MTL_DEBUG_TXSTSFSTS BIT(5)
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#define MTL_DEBUG_TXFSTS BIT(4)
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#define MTL_DEBUG_TWCSTS BIT(3)
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/* MTL debug: Tx FIFO Read Controller Status */
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#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
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#define MTL_DEBUG_TRCSTS_SHIFT 1
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#define MTL_DEBUG_TRCSTS_IDLE 0
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#define MTL_DEBUG_TRCSTS_READ 1
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#define MTL_DEBUG_TRCSTS_TXW 2
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#define MTL_DEBUG_TRCSTS_WRITE 3
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#define MTL_DEBUG_TXPAUSED BIT(0)
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/* MAC debug: GMII or MII Transmit Protocol Engine Status */
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#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
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#define MTL_DEBUG_RXFSTS_SHIFT 4
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#define MTL_DEBUG_RXFSTS_EMPTY 0
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#define MTL_DEBUG_RXFSTS_BT 1
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#define MTL_DEBUG_RXFSTS_AT 2
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#define MTL_DEBUG_RXFSTS_FULL 3
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#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
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#define MTL_DEBUG_RRCSTS_SHIFT 1
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#define MTL_DEBUG_RRCSTS_IDLE 0
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#define MTL_DEBUG_RRCSTS_RDATA 1
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#define MTL_DEBUG_RRCSTS_RSTAT 2
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#define MTL_DEBUG_RRCSTS_FLUSH 3
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#define MTL_DEBUG_RWCSTS BIT(0)
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/* SGMII/RGMII status register */
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#define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
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#define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
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#define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
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#define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
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#define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17)
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#define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17
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#define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19)
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#define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20)
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#define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21)
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/* LNKMOD */
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#define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1
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/* LNKSPEED */
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#define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2
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#define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1
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#define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0
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extern const struct stmmac_dma_ops dwmac4_dma_ops;
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extern const struct stmmac_dma_ops dwmac410_dma_ops;
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#endif /* __DWMAC4_H__ */
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