mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1f9f5201a3
The control register range for clktsio interferes with clkaemifspi clock. And it causes issues for NAND/AEMIF. So fix it. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
427 lines
10 KiB
Plaintext
427 lines
10 KiB
Plaintext
/*
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* Copyright 2013-2014 Texas Instruments, Inc.
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*
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* Keystone 2 Kepler/Hawking SoC clock nodes
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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clocks {
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armpllclk: armpllclk@2620370 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclkarm>;
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clock-output-names = "arm-pll-clk";
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reg = <0x02620370 4>;
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reg-names = "control";
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};
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mainpllclk: mainpllclk@2310110 {
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#clock-cells = <0>;
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compatible = "ti,keystone,main-pll-clock";
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clocks = <&refclksys>;
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reg = <0x02620350 4>, <0x02310110 4>;
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reg-names = "control", "multiplier";
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fixed-postdiv = <2>;
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};
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papllclk: papllclk@2620358 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclkpass>;
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clock-output-names = "pa-pll-clk";
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reg = <0x02620358 4>;
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reg-names = "control";
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};
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ddr3apllclk: ddr3apllclk@2620360 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclkddr3a>;
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clock-output-names = "ddr-3a-pll-clk";
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reg = <0x02620360 4>;
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reg-names = "control";
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};
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ddr3bpllclk: ddr3bpllclk@2620368 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclkddr3b>;
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clock-output-names = "ddr-3b-pll-clk";
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reg = <0x02620368 4>;
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reg-names = "control";
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};
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clktsip: clktsip {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk16>;
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clock-output-names = "tsip";
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reg = <0x02350000 0xb00>, <0x02350000 0x400>;
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reg-names = "control", "domain";
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domain-id = <0>;
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};
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clksrio: clksrio {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1rstiso13>;
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clock-output-names = "srio";
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reg = <0x0235002c 0xb00>, <0x02350010 0x400>;
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reg-names = "control", "domain";
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domain-id = <4>;
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};
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clkhyperlink0: clkhyperlink0 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk12>;
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clock-output-names = "hyperlink-0";
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reg = <0x02350030 0xb00>, <0x02350014 0x400>;
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reg-names = "control", "domain";
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domain-id = <5>;
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};
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clkgem1: clkgem1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem1";
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reg = <0x02350040 0xb00>, <0x02350024 0x400>;
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reg-names = "control", "domain";
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domain-id = <9>;
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};
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clkgem2: clkgem2 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem2";
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reg = <0x02350044 0xb00>, <0x02350028 0x400>;
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reg-names = "control", "domain";
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domain-id = <10>;
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};
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clkgem3: clkgem3 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem3";
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reg = <0x02350048 0xb00>, <0x0235002c 0x400>;
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reg-names = "control", "domain";
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domain-id = <11>;
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};
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clkgem4: clkgem4 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem4";
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reg = <0x0235004c 0xb00>, <0x02350030 0x400>;
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reg-names = "control", "domain";
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domain-id = <12>;
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};
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clkgem5: clkgem5 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem5";
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reg = <0x02350050 0xb00>, <0x02350034 0x400>;
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reg-names = "control", "domain";
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domain-id = <13>;
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};
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clkgem6: clkgem6 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem6";
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reg = <0x02350054 0xb00>, <0x02350038 0x400>;
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reg-names = "control", "domain";
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domain-id = <14>;
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};
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clkgem7: clkgem7 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk1>;
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clock-output-names = "gem7";
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reg = <0x02350058 0xb00>, <0x0235003c 0x400>;
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reg-names = "control", "domain";
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domain-id = <15>;
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};
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clkddr31: clkddr31 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "ddr3-1";
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reg = <0x02350060 0xb00>, <0x02350040 0x400>;
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reg-names = "control", "domain";
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domain-id = <16>;
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};
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clktac: clktac {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "tac";
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reg = <0x02350064 0xb00>, <0x02350044 0x400>;
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reg-names = "control", "domain";
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domain-id = <17>;
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};
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clkrac01: clkrac01 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "rac-01";
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reg = <0x02350068 0xb00>, <0x02350044 0x400>;
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reg-names = "control", "domain";
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domain-id = <17>;
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};
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clkrac23: clkrac23 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "rac-23";
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reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
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reg-names = "control", "domain";
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domain-id = <18>;
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};
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clkfftc0: clkfftc0 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "fftc-0";
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reg = <0x02350070 0xb00>, <0x0235004c 0x400>;
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reg-names = "control", "domain";
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domain-id = <19>;
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};
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clkfftc1: clkfftc1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "fftc-1";
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reg = <0x02350074 0xb00>, <0x0235004c 0x400>;
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reg-names = "control", "domain";
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domain-id = <19>;
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};
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clkfftc2: clkfftc2 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "fftc-2";
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reg = <0x02350078 0xb00>, <0x02350050 0x400>;
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reg-names = "control", "domain";
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domain-id = <20>;
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};
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clkfftc3: clkfftc3 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "fftc-3";
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reg = <0x0235007c 0xb00>, <0x02350050 0x400>;
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reg-names = "control", "domain";
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domain-id = <20>;
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};
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clkfftc4: clkfftc4 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "fftc-4";
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reg = <0x02350080 0xb00>, <0x02350050 0x400>;
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reg-names = "control", "domain";
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domain-id = <20>;
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};
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clkfftc5: clkfftc5 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "fftc-5";
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reg = <0x02350084 0xb00>, <0x02350050 0x400>;
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reg-names = "control", "domain";
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domain-id = <20>;
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};
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clkaif: clkaif {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "aif";
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reg = <0x02350088 0xb00>, <0x02350054 0x400>;
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reg-names = "control", "domain";
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domain-id = <21>;
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};
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clktcp3d0: clktcp3d0 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "tcp3d-0";
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reg = <0x0235008c 0xb00>, <0x02350058 0x400>;
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reg-names = "control", "domain";
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domain-id = <22>;
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};
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clktcp3d1: clktcp3d1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "tcp3d-1";
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reg = <0x02350090 0xb00>, <0x02350058 0x400>;
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reg-names = "control", "domain";
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domain-id = <22>;
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};
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clktcp3d2: clktcp3d2 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "tcp3d-2";
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reg = <0x02350094 0xb00>, <0x0235005c 0x400>;
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reg-names = "control", "domain";
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domain-id = <23>;
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};
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clktcp3d3: clktcp3d3 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "tcp3d-3";
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reg = <0x02350098 0xb00>, <0x0235005c 0x400>;
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reg-names = "control", "domain";
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domain-id = <23>;
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};
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clkvcp0: clkvcp0 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "vcp-0";
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reg = <0x0235009c 0xb00>, <0x02350060 0x400>;
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reg-names = "control", "domain";
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domain-id = <24>;
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};
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clkvcp1: clkvcp1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "vcp-1";
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reg = <0x023500a0 0xb00>, <0x02350060 0x400>;
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reg-names = "control", "domain";
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domain-id = <24>;
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};
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clkvcp2: clkvcp2 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "vcp-2";
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reg = <0x023500a4 0xb00>, <0x02350060 0x400>;
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reg-names = "control", "domain";
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domain-id = <24>;
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};
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clkvcp3: clkvcp3 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "vcp-3";
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reg = <0x023500a8 0xb00>, <0x02350060 0x400>;
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reg-names = "control", "domain";
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domain-id = <24>;
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};
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clkvcp4: clkvcp4 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "vcp-4";
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reg = <0x023500ac 0xb00>, <0x02350064 0x400>;
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reg-names = "control", "domain";
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domain-id = <25>;
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};
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clkvcp5: clkvcp5 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "vcp-5";
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reg = <0x023500b0 0xb00>, <0x02350064 0x400>;
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reg-names = "control", "domain";
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domain-id = <25>;
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};
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clkvcp6: clkvcp6 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "vcp-6";
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reg = <0x023500b4 0xb00>, <0x02350064 0x400>;
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reg-names = "control", "domain";
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domain-id = <25>;
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};
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clkvcp7: clkvcp7 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "vcp-7";
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reg = <0x023500b8 0xb00>, <0x02350064 0x400>;
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reg-names = "control", "domain";
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domain-id = <25>;
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};
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clkbcp: clkbcp {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "bcp";
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reg = <0x023500bc 0xb00>, <0x02350068 0x400>;
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reg-names = "control", "domain";
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domain-id = <26>;
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};
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clkdxb: clkdxb {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "dxb";
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reg = <0x023500c0 0xb00>, <0x0235006c 0x400>;
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reg-names = "control", "domain";
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domain-id = <27>;
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};
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clkhyperlink1: clkhyperlink1 {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk12>;
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clock-output-names = "hyperlink-1";
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reg = <0x023500c4 0xb00>, <0x02350070 0x400>;
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reg-names = "control", "domain";
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domain-id = <28>;
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};
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clkxge: clkxge {
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#clock-cells = <0>;
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compatible = "ti,keystone,psc-clock";
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clocks = <&chipclk13>;
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clock-output-names = "xge";
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reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
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reg-names = "control", "domain";
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domain-id = <29>;
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};
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};
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