mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 11:58:21 +07:00
19d52e94e0
This series of changes mostly configures the cameras for dra7 and am437x that have been pending for few months now because of waiting for clock dependencies to clear. So these changes are based on earlier dts changes with with Tero Kristo's for-5.6-ti-clk branch merged in. Then there's a series of changes to configure powervr sgx target module for am335x, am437x and dra7 that have been waiting to have the rstctrl reset driver dependencies to clear. Also included are few minor patches to configure 1-wire and coulomb counter calibration interrupt for droid4. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl4rTjIRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXNPIxAAsx6cR/yzoEvUv1fGFi44Y/VZEhfI/8yT 5esGWql/UINkyTLBTsME6liDTt7rAVxcHH1JQj04hYH/w/PQU8S4iu8ZVwxoAb9R Mmnfn8Py26scney0zseJc6tTTDbtXF+mxDBYUqAJNKjDyoRkJKxWtMMOHUC7WjVW P5E4uWgi2ydEFgn6hOzLORgHPtNnOWPdXYzKvmum7VZdRny7KHcuOk4kVFnj3dzG RwGrsOQcs2EyHd08n+U3tZqk34JqhOWi2VAKPZTHVlsZOdDKU9hm45ZSDh/j7Xoy 74x2ux81guKBAtgpKSJR5TUottgPM5IdnnyCmKkDgF7AWySByeJYPOVWyxwZuSQD tCmCi9fFSXCogoijMvSFPbcsKI/u6UKHYIOS9zvJo70FxNVTckhzjTH+DRQpjrTB oEAfpCS56bHUUYvPomDvxRT87kLlcs/A6g8+puRKd2xa3dmsXkTKeppuEBIC6WKE JtZYGsvWSe0gSVscsrE3Ecf17jS2O7Yhy3/4eOHJzUgsIGn8xcjuJJO3Av+bFj87 kDF66tRKR6LcKD1S6v5a87hmKD3rxkj23LUEvS0bWsOVLmgqIQYeZYpR5ujkRLxC 1NlzWFVqBtCMe6qPRz7FaitrdZlTaMURRD0GXSQmZCsTrSVrghUTJBZw92ep2kWD rIwSzpB1p08= =u4PK -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.6/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late Late omap dts changes for v5.6 merge window This series of changes mostly configures the cameras for dra7 and am437x that have been pending for few months now because of waiting for clock dependencies to clear. So these changes are based on earlier dts changes with with Tero Kristo's for-5.6-ti-clk branch merged in. Then there's a series of changes to configure powervr sgx target module for am335x, am437x and dra7 that have been waiting to have the rstctrl reset driver dependencies to clear. Also included are few minor patches to configure 1-wire and coulomb counter calibration interrupt for droid4. * tag 'omap-for-v5.6/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (25 commits) ARM: dts: omap4-droid4: Enable hdq for droid4 ds250x 1-wire battery nvmem ARM: dts: motorola-cpcap-mapphone: Configure calibration interrupt ARM: dts: Configure interconnect target module for am437x sgx ARM: dts: Configure sgx for dra7 ARM: dts: Configure rstctrl reset for am335x SGX ARM: dts: dra7: Add ti-sysc node for VPE ARM: dts: dra7: add vpe clkctrl node ARM: dts: am43x-epos-evm: Add VPFE and OV2659 entries ARM: dts: am437x-sk-evm: Add VPFE and OV2659 entries ARM: dts: am43xx: add support for clkout1 clock arm: dts: dra76-evm: Add CAL and OV5640 nodes arm: dtsi: dra76x: Add CAL dtsi node arm: dts: dra72-evm-common: Add entries for the CSI2 cameras ARM: dts: DRA72: Add CAL dtsi node ARM: dts: dra7-l4: Add ti-sysc node for CAM ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only ARM: dts: dra7: add cam clkctrl node ARM: dts: Add omap3-echo ARM: dts: Add dtsi files for AM3703, AM3715 and DM3725 ARM: dts: am335x-icev2: Add support for OSD9616P0899-10 at i2c0 ... Link: https://lore.kernel.org/r/pull-1579896427-50330@atomide.com-3 Signed-off-by: Olof Johansson <olof@lixom.net>
4653 lines
137 KiB
Plaintext
4653 lines
137 KiB
Plaintext
&l4_cfg { /* 0x4a000000 */
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compatible = "ti,dra7-l4-cfg", "simple-bus";
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reg = <0x4a000000 0x800>,
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<0x4a000800 0x800>,
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<0x4a001000 0x1000>;
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reg-names = "ap", "la", "ia0";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
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<0x00100000 0x4a100000 0x100000>, /* segment 1 */
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<0x00200000 0x4a200000 0x100000>; /* segment 2 */
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segment@0 { /* 0x4a000000 */
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
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<0x00000800 0x00000800 0x000800>, /* ap 1 */
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<0x00001000 0x00001000 0x001000>, /* ap 2 */
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<0x00002000 0x00002000 0x002000>, /* ap 3 */
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<0x00004000 0x00004000 0x001000>, /* ap 4 */
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<0x00005000 0x00005000 0x001000>, /* ap 5 */
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<0x00006000 0x00006000 0x001000>, /* ap 6 */
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<0x00008000 0x00008000 0x002000>, /* ap 7 */
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<0x0000a000 0x0000a000 0x001000>, /* ap 8 */
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<0x00056000 0x00056000 0x001000>, /* ap 9 */
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<0x00057000 0x00057000 0x001000>, /* ap 10 */
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<0x0005e000 0x0005e000 0x002000>, /* ap 11 */
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<0x00060000 0x00060000 0x001000>, /* ap 12 */
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<0x00080000 0x00080000 0x008000>, /* ap 13 */
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<0x00088000 0x00088000 0x001000>, /* ap 14 */
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<0x000a0000 0x000a0000 0x008000>, /* ap 15 */
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<0x000a8000 0x000a8000 0x001000>, /* ap 16 */
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<0x000d9000 0x000d9000 0x001000>, /* ap 17 */
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<0x000da000 0x000da000 0x001000>, /* ap 18 */
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<0x000dd000 0x000dd000 0x001000>, /* ap 19 */
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<0x000de000 0x000de000 0x001000>, /* ap 20 */
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<0x000e0000 0x000e0000 0x001000>, /* ap 21 */
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<0x000e1000 0x000e1000 0x001000>, /* ap 22 */
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<0x000f4000 0x000f4000 0x001000>, /* ap 23 */
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<0x000f5000 0x000f5000 0x001000>, /* ap 24 */
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<0x000f6000 0x000f6000 0x001000>, /* ap 25 */
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<0x000f7000 0x000f7000 0x001000>, /* ap 26 */
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<0x00090000 0x00090000 0x008000>, /* ap 59 */
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<0x00098000 0x00098000 0x001000>; /* ap 60 */
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target-module@2000 { /* 0x4a002000, ap 3 08.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x2000 0x4>;
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reg-names = "rev";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2000 0x2000>;
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scm: scm@0 {
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compatible = "ti,dra7-scm-core", "simple-bus";
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reg = <0 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x2000>;
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scm_conf: scm_conf@0 {
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compatible = "syscon", "simple-bus";
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reg = <0x0 0x1400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x1400>;
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pbias_regulator: pbias_regulator@e00 {
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compatible = "ti,pbias-dra7", "ti,pbias-omap";
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reg = <0xe00 0x4>;
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syscon = <&scm_conf>;
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pbias_mmc_reg: pbias_mmc_omap5 {
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regulator-name = "pbias_mmc_omap5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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phy_gmii_sel: phy-gmii-sel {
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compatible = "ti,dra7xx-phy-gmii-sel";
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reg = <0x554 0x4>;
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#phy-cells = <1>;
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};
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scm_conf_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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dra7_pmx_core: pinmux@1400 {
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compatible = "ti,dra7-padconf",
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"pinctrl-single";
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reg = <0x1400 0x0468>;
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#address-cells = <1>;
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#size-cells = <0>;
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#pinctrl-cells = <1>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x3fffffff>;
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};
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scm_conf1: scm_conf@1c04 {
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compatible = "syscon";
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reg = <0x1c04 0x0020>;
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#syscon-cells = <2>;
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};
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scm_conf_pcie: scm_conf@1c24 {
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compatible = "syscon";
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reg = <0x1c24 0x0024>;
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};
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sdma_xbar: dma-router@b78 {
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compatible = "ti,dra7-dma-crossbar";
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reg = <0xb78 0xfc>;
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#dma-cells = <1>;
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dma-requests = <205>;
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ti,dma-safe-map = <0>;
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dma-masters = <&sdma>;
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};
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edma_xbar: dma-router@c78 {
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compatible = "ti,dra7-dma-crossbar";
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reg = <0xc78 0x7c>;
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#dma-cells = <2>;
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dma-requests = <204>;
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ti,dma-safe-map = <0>;
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dma-masters = <&edma>;
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};
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};
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};
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target-module@5000 { /* 0x4a005000, ap 5 10.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x5000 0x4>;
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reg-names = "rev";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x5000 0x1000>;
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cm_core_aon: cm_core_aon@0 {
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compatible = "ti,dra7-cm-core-aon",
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"simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0 0x2000>;
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ranges = <0 0 0x2000>;
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cm_core_aon_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cm_core_aon_clockdomains: clockdomains {
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};
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};
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};
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target-module@8000 { /* 0x4a008000, ap 7 0e.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x8000 0x4>;
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reg-names = "rev";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x8000 0x2000>;
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cm_core: cm_core@0 {
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compatible = "ti,dra7-cm-core", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0 0x3000>;
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ranges = <0 0 0x3000>;
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cm_core_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cm_core_clockdomains: clockdomains {
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};
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};
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};
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target-module@56000 { /* 0x4a056000, ap 9 02.0 */
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x56000 0x4>,
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<0x5602c 0x4>,
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<0x56028 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
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SYSC_OMAP2_EMUFREE |
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SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-midle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>,
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<SYSC_IDLE_SMART_WKUP>;
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ti,syss-mask = <1>;
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/* Domains (P, C): core_pwrdm, dma_clkdm */
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clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x56000 0x1000>;
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sdma: dma-controller@0 {
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compatible = "ti,omap4430-sdma", "ti,omap-sdma";
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reg = <0x0 0x1000>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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dma-channels = <32>;
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dma-requests = <127>;
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};
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};
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target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */
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compatible = "ti,sysc";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x5e000 0x2000>;
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};
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target-module@80000 { /* 0x4a080000, ap 13 20.0 */
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x80000 0x4>,
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<0x80010 0x4>,
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<0x80014 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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/* Domains (P, C): l3init_pwrdm, l3init_clkdm */
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clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x80000 0x8000>;
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ocp2scp@0 {
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compatible = "ti,omap-ocp2scp";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x8000>;
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reg = <0x0 0x20>;
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usb2_phy1: phy@4000 {
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compatible = "ti,dra7x-usb2", "ti,omap-usb2";
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reg = <0x4000 0x400>;
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syscon-phy-power = <&scm_conf 0x300>;
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clocks = <&usb_phy1_always_on_clk32k>,
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<&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
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clock-names = "wkupclk",
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"refclk";
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#phy-cells = <0>;
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};
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usb2_phy2: phy@5000 {
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compatible = "ti,dra7x-usb2-phy2",
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"ti,omap-usb2";
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reg = <0x5000 0x400>;
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syscon-phy-power = <&scm_conf 0xe74>;
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clocks = <&usb_phy2_always_on_clk32k>,
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<&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
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clock-names = "wkupclk",
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"refclk";
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#phy-cells = <0>;
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};
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usb3_phy1: phy@4400 {
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compatible = "ti,omap-usb3";
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reg = <0x4400 0x80>,
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<0x4800 0x64>,
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<0x4c00 0x40>;
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reg-names = "phy_rx", "phy_tx", "pll_ctrl";
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syscon-phy-power = <&scm_conf 0x370>;
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clocks = <&usb_phy3_always_on_clk32k>,
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<&sys_clkin1>,
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<&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
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clock-names = "wkupclk",
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"sysclk",
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"refclk";
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#phy-cells = <0>;
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};
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};
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};
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target-module@90000 { /* 0x4a090000, ap 59 42.0 */
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x90000 0x4>,
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<0x90010 0x4>,
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<0x90014 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE)>;
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,syss-mask = <1>;
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/* Domains (P, C): l3init_pwrdm, l3init_clkdm */
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clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
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clock-names = "fck";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x90000 0x8000>;
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ocp2scp@0 {
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compatible = "ti,omap-ocp2scp";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x8000>;
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reg = <0x0 0x20>;
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pcie1_phy: pciephy@4000 {
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compatible = "ti,phy-pipe3-pcie";
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reg = <0x4000 0x80>, /* phy_rx */
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<0x4400 0x64>; /* phy_tx */
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reg-names = "phy_rx", "phy_tx";
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syscon-phy-power = <&scm_conf_pcie 0x1c>;
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syscon-pcs = <&scm_conf_pcie 0x10>;
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clocks = <&dpll_pcie_ref_ck>,
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<&dpll_pcie_ref_m2ldo_ck>,
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<&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
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<&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
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<&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
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<&optfclk_pciephy_div>,
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<&sys_clkin1>;
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clock-names = "dpll_ref", "dpll_ref_m2",
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"wkupclk", "refclk",
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"div-clk", "phy-div", "sysclk";
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#phy-cells = <0>;
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};
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pcie2_phy: pciephy@5000 {
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compatible = "ti,phy-pipe3-pcie";
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reg = <0x5000 0x80>, /* phy_rx */
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<0x5400 0x64>; /* phy_tx */
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reg-names = "phy_rx", "phy_tx";
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syscon-phy-power = <&scm_conf_pcie 0x20>;
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syscon-pcs = <&scm_conf_pcie 0x10>;
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clocks = <&dpll_pcie_ref_ck>,
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<&dpll_pcie_ref_m2ldo_ck>,
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<&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
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<&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
|
|
<&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
|
|
<&optfclk_pciephy_div>,
|
|
<&sys_clkin1>;
|
|
clock-names = "dpll_ref", "dpll_ref_m2",
|
|
"wkupclk", "refclk",
|
|
"div-clk", "phy-div", "sysclk";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sata_phy: phy@6000 {
|
|
compatible = "ti,phy-pipe3-sata";
|
|
reg = <0x6000 0x80>, /* phy_rx */
|
|
<0x6400 0x64>, /* phy_tx */
|
|
<0x6800 0x40>; /* pll_ctrl */
|
|
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
|
syscon-phy-power = <&scm_conf 0x374>;
|
|
clocks = <&sys_clkin1>,
|
|
<&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
|
|
clock-names = "sysclk", "refclk";
|
|
syscon-pllreset = <&scm_conf 0x3fc>;
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xa0000 0x8000>;
|
|
};
|
|
|
|
target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
|
|
compatible = "ti,sysc-omap4-sr", "ti,sysc";
|
|
reg = <0xd9038 0x4>;
|
|
reg-names = "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
|
|
clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xd9000 0x1000>;
|
|
|
|
/* SmartReflex child device marked reserved in TRM */
|
|
};
|
|
|
|
target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
|
|
compatible = "ti,sysc-omap4-sr", "ti,sysc";
|
|
reg = <0xdd038 0x4>;
|
|
reg-names = "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
|
|
clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xdd000 0x1000>;
|
|
|
|
/* SmartReflex child device marked reserved in TRM */
|
|
};
|
|
|
|
target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xe0000 0x1000>;
|
|
};
|
|
|
|
target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0xf4000 0x4>,
|
|
<0xf4010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xf4000 0x1000>;
|
|
|
|
mailbox1: mailbox@0 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
ti,mbox-num-users = <3>;
|
|
ti,mbox-num-fifos = <8>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0xf6000 0x4>,
|
|
<0xf6010 0x4>,
|
|
<0xf6014 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xf6000 0x1000>;
|
|
|
|
hwspinlock: spinlock@0 {
|
|
compatible = "ti,omap4-hwspinlock";
|
|
reg = <0x0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
segment@100000 { /* 0x4a100000 */
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */
|
|
<0x00003000 0x00103000 0x001000>, /* ap 28 */
|
|
<0x00008000 0x00108000 0x001000>, /* ap 29 */
|
|
<0x00009000 0x00109000 0x001000>, /* ap 30 */
|
|
<0x00040000 0x00140000 0x010000>, /* ap 31 */
|
|
<0x00050000 0x00150000 0x001000>, /* ap 32 */
|
|
<0x00051000 0x00151000 0x001000>, /* ap 33 */
|
|
<0x00052000 0x00152000 0x001000>, /* ap 34 */
|
|
<0x00053000 0x00153000 0x001000>, /* ap 35 */
|
|
<0x00054000 0x00154000 0x001000>, /* ap 36 */
|
|
<0x00055000 0x00155000 0x001000>, /* ap 37 */
|
|
<0x00056000 0x00156000 0x001000>, /* ap 38 */
|
|
<0x00057000 0x00157000 0x001000>, /* ap 39 */
|
|
<0x00058000 0x00158000 0x001000>, /* ap 40 */
|
|
<0x0005b000 0x0015b000 0x001000>, /* ap 41 */
|
|
<0x0005c000 0x0015c000 0x001000>, /* ap 42 */
|
|
<0x0005d000 0x0015d000 0x001000>, /* ap 45 */
|
|
<0x0005e000 0x0015e000 0x001000>, /* ap 46 */
|
|
<0x0005f000 0x0015f000 0x001000>, /* ap 47 */
|
|
<0x00060000 0x00160000 0x001000>, /* ap 48 */
|
|
<0x00061000 0x00161000 0x001000>, /* ap 49 */
|
|
<0x00062000 0x00162000 0x001000>, /* ap 50 */
|
|
<0x00063000 0x00163000 0x001000>, /* ap 51 */
|
|
<0x00064000 0x00164000 0x001000>, /* ap 52 */
|
|
<0x00065000 0x00165000 0x001000>, /* ap 53 */
|
|
<0x00066000 0x00166000 0x001000>, /* ap 54 */
|
|
<0x00067000 0x00167000 0x001000>, /* ap 55 */
|
|
<0x00068000 0x00168000 0x001000>, /* ap 56 */
|
|
<0x0006d000 0x0016d000 0x001000>, /* ap 57 */
|
|
<0x0006e000 0x0016e000 0x001000>, /* ap 58 */
|
|
<0x00071000 0x00171000 0x001000>, /* ap 61 */
|
|
<0x00072000 0x00172000 0x001000>, /* ap 62 */
|
|
<0x00073000 0x00173000 0x001000>, /* ap 63 */
|
|
<0x00074000 0x00174000 0x001000>, /* ap 64 */
|
|
<0x00075000 0x00175000 0x001000>, /* ap 65 */
|
|
<0x00076000 0x00176000 0x001000>, /* ap 66 */
|
|
<0x00077000 0x00177000 0x001000>, /* ap 67 */
|
|
<0x00078000 0x00178000 0x001000>, /* ap 68 */
|
|
<0x00081000 0x00181000 0x001000>, /* ap 69 */
|
|
<0x00082000 0x00182000 0x001000>, /* ap 70 */
|
|
<0x00083000 0x00183000 0x001000>, /* ap 71 */
|
|
<0x00084000 0x00184000 0x001000>, /* ap 72 */
|
|
<0x00085000 0x00185000 0x001000>, /* ap 73 */
|
|
<0x00086000 0x00186000 0x001000>, /* ap 74 */
|
|
<0x00087000 0x00187000 0x001000>, /* ap 75 */
|
|
<0x00088000 0x00188000 0x001000>, /* ap 76 */
|
|
<0x00069000 0x00169000 0x001000>, /* ap 103 */
|
|
<0x0006a000 0x0016a000 0x001000>, /* ap 104 */
|
|
<0x00079000 0x00179000 0x001000>, /* ap 105 */
|
|
<0x0007a000 0x0017a000 0x001000>, /* ap 106 */
|
|
<0x0006b000 0x0016b000 0x001000>, /* ap 107 */
|
|
<0x0006c000 0x0016c000 0x001000>, /* ap 108 */
|
|
<0x0007b000 0x0017b000 0x001000>, /* ap 121 */
|
|
<0x0007c000 0x0017c000 0x001000>, /* ap 122 */
|
|
<0x0007d000 0x0017d000 0x001000>, /* ap 123 */
|
|
<0x0007e000 0x0017e000 0x001000>, /* ap 124 */
|
|
<0x00059000 0x00159000 0x001000>, /* ap 125 */
|
|
<0x0005a000 0x0015a000 0x001000>; /* ap 126 */
|
|
|
|
target-module@2000 { /* 0x4a102000, ap 27 3c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x2000 0x1000>;
|
|
};
|
|
|
|
target-module@8000 { /* 0x4a108000, ap 29 1e.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x8000 0x1000>;
|
|
};
|
|
|
|
target-module@40000 { /* 0x4a140000, ap 31 06.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x40000 0x10000>;
|
|
};
|
|
|
|
target-module@51000 { /* 0x4a151000, ap 33 50.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x51000 0x1000>;
|
|
};
|
|
|
|
target-module@53000 { /* 0x4a153000, ap 35 54.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x53000 0x1000>;
|
|
};
|
|
|
|
target-module@55000 { /* 0x4a155000, ap 37 46.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x55000 0x1000>;
|
|
};
|
|
|
|
target-module@57000 { /* 0x4a157000, ap 39 58.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x57000 0x1000>;
|
|
};
|
|
|
|
target-module@59000 { /* 0x4a159000, ap 125 6a.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x59000 0x1000>;
|
|
};
|
|
|
|
target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x5b000 0x1000>;
|
|
};
|
|
|
|
target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x5d000 0x1000>;
|
|
};
|
|
|
|
target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x5f000 0x1000>;
|
|
};
|
|
|
|
target-module@61000 { /* 0x4a161000, ap 49 32.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x61000 0x1000>;
|
|
};
|
|
|
|
target-module@63000 { /* 0x4a163000, ap 51 5c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x63000 0x1000>;
|
|
};
|
|
|
|
target-module@65000 { /* 0x4a165000, ap 53 4e.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x65000 0x1000>;
|
|
};
|
|
|
|
target-module@67000 { /* 0x4a167000, ap 55 5e.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x67000 0x1000>;
|
|
};
|
|
|
|
target-module@69000 { /* 0x4a169000, ap 103 4a.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x69000 0x1000>;
|
|
};
|
|
|
|
target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x6b000 0x1000>;
|
|
};
|
|
|
|
target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x6d000 0x1000>;
|
|
};
|
|
|
|
target-module@71000 { /* 0x4a171000, ap 61 48.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x71000 0x1000>;
|
|
};
|
|
|
|
target-module@73000 { /* 0x4a173000, ap 63 2a.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x73000 0x1000>;
|
|
};
|
|
|
|
target-module@75000 { /* 0x4a175000, ap 65 64.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x75000 0x1000>;
|
|
};
|
|
|
|
target-module@77000 { /* 0x4a177000, ap 67 66.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x77000 0x1000>;
|
|
};
|
|
|
|
target-module@79000 { /* 0x4a179000, ap 105 34.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x79000 0x1000>;
|
|
};
|
|
|
|
target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x7b000 0x1000>;
|
|
};
|
|
|
|
target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x7d000 0x1000>;
|
|
};
|
|
|
|
target-module@81000 { /* 0x4a181000, ap 69 26.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x81000 0x1000>;
|
|
};
|
|
|
|
target-module@83000 { /* 0x4a183000, ap 71 2e.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x83000 0x1000>;
|
|
};
|
|
|
|
target-module@85000 { /* 0x4a185000, ap 73 36.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x85000 0x1000>;
|
|
};
|
|
|
|
target-module@87000 { /* 0x4a187000, ap 75 74.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x87000 0x1000>;
|
|
};
|
|
};
|
|
|
|
segment@200000 { /* 0x4a200000 */
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */
|
|
<0x00019000 0x00219000 0x001000>, /* ap 44 */
|
|
<0x00000000 0x00200000 0x001000>, /* ap 77 */
|
|
<0x00001000 0x00201000 0x001000>, /* ap 78 */
|
|
<0x0000a000 0x0020a000 0x001000>, /* ap 79 */
|
|
<0x0000b000 0x0020b000 0x001000>, /* ap 80 */
|
|
<0x0000c000 0x0020c000 0x001000>, /* ap 81 */
|
|
<0x0000d000 0x0020d000 0x001000>, /* ap 82 */
|
|
<0x0000e000 0x0020e000 0x001000>, /* ap 83 */
|
|
<0x0000f000 0x0020f000 0x001000>, /* ap 84 */
|
|
<0x00010000 0x00210000 0x001000>, /* ap 85 */
|
|
<0x00011000 0x00211000 0x001000>, /* ap 86 */
|
|
<0x00012000 0x00212000 0x001000>, /* ap 87 */
|
|
<0x00013000 0x00213000 0x001000>, /* ap 88 */
|
|
<0x00014000 0x00214000 0x001000>, /* ap 89 */
|
|
<0x00015000 0x00215000 0x001000>, /* ap 90 */
|
|
<0x0002a000 0x0022a000 0x001000>, /* ap 91 */
|
|
<0x0002b000 0x0022b000 0x001000>, /* ap 92 */
|
|
<0x0001c000 0x0021c000 0x001000>, /* ap 93 */
|
|
<0x0001d000 0x0021d000 0x001000>, /* ap 94 */
|
|
<0x0001e000 0x0021e000 0x001000>, /* ap 95 */
|
|
<0x0001f000 0x0021f000 0x001000>, /* ap 96 */
|
|
<0x00020000 0x00220000 0x001000>, /* ap 97 */
|
|
<0x00021000 0x00221000 0x001000>, /* ap 98 */
|
|
<0x00024000 0x00224000 0x001000>, /* ap 99 */
|
|
<0x00025000 0x00225000 0x001000>, /* ap 100 */
|
|
<0x00026000 0x00226000 0x001000>, /* ap 101 */
|
|
<0x00027000 0x00227000 0x001000>, /* ap 102 */
|
|
<0x0002c000 0x0022c000 0x001000>, /* ap 109 */
|
|
<0x0002d000 0x0022d000 0x001000>, /* ap 110 */
|
|
<0x0002e000 0x0022e000 0x001000>, /* ap 111 */
|
|
<0x0002f000 0x0022f000 0x001000>, /* ap 112 */
|
|
<0x00030000 0x00230000 0x001000>, /* ap 113 */
|
|
<0x00031000 0x00231000 0x001000>, /* ap 114 */
|
|
<0x00032000 0x00232000 0x001000>, /* ap 115 */
|
|
<0x00033000 0x00233000 0x001000>, /* ap 116 */
|
|
<0x00034000 0x00234000 0x001000>, /* ap 117 */
|
|
<0x00035000 0x00235000 0x001000>, /* ap 118 */
|
|
<0x00036000 0x00236000 0x001000>, /* ap 119 */
|
|
<0x00037000 0x00237000 0x001000>, /* ap 120 */
|
|
<0x0001a000 0x0021a000 0x001000>, /* ap 127 */
|
|
<0x0001b000 0x0021b000 0x001000>; /* ap 128 */
|
|
|
|
target-module@0 { /* 0x4a200000, ap 77 3e.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0x1000>;
|
|
};
|
|
|
|
target-module@a000 { /* 0x4a20a000, ap 79 30.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xa000 0x1000>;
|
|
};
|
|
|
|
target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xc000 0x1000>;
|
|
};
|
|
|
|
target-module@e000 { /* 0x4a20e000, ap 83 22.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xe000 0x1000>;
|
|
};
|
|
|
|
target-module@10000 { /* 0x4a210000, ap 85 14.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x10000 0x1000>;
|
|
};
|
|
|
|
target-module@12000 { /* 0x4a212000, ap 87 16.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x12000 0x1000>;
|
|
};
|
|
|
|
target-module@14000 { /* 0x4a214000, ap 89 1c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x14000 0x1000>;
|
|
};
|
|
|
|
target-module@18000 { /* 0x4a218000, ap 43 12.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x18000 0x1000>;
|
|
};
|
|
|
|
target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x1a000 0x1000>;
|
|
};
|
|
|
|
target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x1c000 0x1000>;
|
|
};
|
|
|
|
target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x1e000 0x1000>;
|
|
};
|
|
|
|
target-module@20000 { /* 0x4a220000, ap 97 24.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x20000 0x1000>;
|
|
};
|
|
|
|
target-module@24000 { /* 0x4a224000, ap 99 44.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x24000 0x1000>;
|
|
};
|
|
|
|
target-module@26000 { /* 0x4a226000, ap 101 2c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x26000 0x1000>;
|
|
};
|
|
|
|
target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x2a000 0x1000>;
|
|
};
|
|
|
|
target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x2c000 0x1000>;
|
|
};
|
|
|
|
target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x2e000 0x1000>;
|
|
};
|
|
|
|
target-module@30000 { /* 0x4a230000, ap 113 70.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x30000 0x1000>;
|
|
};
|
|
|
|
target-module@32000 { /* 0x4a232000, ap 115 5a.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x32000 0x1000>;
|
|
};
|
|
|
|
target-module@34000 { /* 0x4a234000, ap 117 76.1 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x34000 0x1000>;
|
|
};
|
|
|
|
target-module@36000 { /* 0x4a236000, ap 119 62.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x36000 0x1000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&l4_per1 { /* 0x48000000 */
|
|
compatible = "ti,dra7-l4-per1", "simple-bus";
|
|
reg = <0x48000000 0x800>,
|
|
<0x48000800 0x800>,
|
|
<0x48001000 0x400>,
|
|
<0x48001400 0x400>,
|
|
<0x48001800 0x400>,
|
|
<0x48001c00 0x400>;
|
|
reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
|
|
<0x00200000 0x48200000 0x200000>; /* segment 1 */
|
|
|
|
segment@0 { /* 0x48000000 */
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
|
|
<0x00001000 0x00001000 0x000400>, /* ap 1 */
|
|
<0x00000800 0x00000800 0x000800>, /* ap 2 */
|
|
<0x00020000 0x00020000 0x001000>, /* ap 3 */
|
|
<0x00021000 0x00021000 0x001000>, /* ap 4 */
|
|
<0x00032000 0x00032000 0x001000>, /* ap 5 */
|
|
<0x00033000 0x00033000 0x001000>, /* ap 6 */
|
|
<0x00034000 0x00034000 0x001000>, /* ap 7 */
|
|
<0x00035000 0x00035000 0x001000>, /* ap 8 */
|
|
<0x00036000 0x00036000 0x001000>, /* ap 9 */
|
|
<0x00037000 0x00037000 0x001000>, /* ap 10 */
|
|
<0x0003e000 0x0003e000 0x001000>, /* ap 11 */
|
|
<0x0003f000 0x0003f000 0x001000>, /* ap 12 */
|
|
<0x00055000 0x00055000 0x001000>, /* ap 13 */
|
|
<0x00056000 0x00056000 0x001000>, /* ap 14 */
|
|
<0x00057000 0x00057000 0x001000>, /* ap 15 */
|
|
<0x00058000 0x00058000 0x001000>, /* ap 16 */
|
|
<0x00059000 0x00059000 0x001000>, /* ap 17 */
|
|
<0x0005a000 0x0005a000 0x001000>, /* ap 18 */
|
|
<0x0005b000 0x0005b000 0x001000>, /* ap 19 */
|
|
<0x0005c000 0x0005c000 0x001000>, /* ap 20 */
|
|
<0x0005d000 0x0005d000 0x001000>, /* ap 21 */
|
|
<0x0005e000 0x0005e000 0x001000>, /* ap 22 */
|
|
<0x00060000 0x00060000 0x001000>, /* ap 23 */
|
|
<0x0006a000 0x0006a000 0x001000>, /* ap 24 */
|
|
<0x0006b000 0x0006b000 0x001000>, /* ap 25 */
|
|
<0x0006c000 0x0006c000 0x001000>, /* ap 26 */
|
|
<0x0006d000 0x0006d000 0x001000>, /* ap 27 */
|
|
<0x0006e000 0x0006e000 0x001000>, /* ap 28 */
|
|
<0x0006f000 0x0006f000 0x001000>, /* ap 29 */
|
|
<0x00070000 0x00070000 0x001000>, /* ap 30 */
|
|
<0x00071000 0x00071000 0x001000>, /* ap 31 */
|
|
<0x00072000 0x00072000 0x001000>, /* ap 32 */
|
|
<0x00073000 0x00073000 0x001000>, /* ap 33 */
|
|
<0x00061000 0x00061000 0x001000>, /* ap 34 */
|
|
<0x00053000 0x00053000 0x001000>, /* ap 35 */
|
|
<0x00054000 0x00054000 0x001000>, /* ap 36 */
|
|
<0x000b2000 0x000b2000 0x001000>, /* ap 37 */
|
|
<0x000b3000 0x000b3000 0x001000>, /* ap 38 */
|
|
<0x00078000 0x00078000 0x001000>, /* ap 39 */
|
|
<0x00079000 0x00079000 0x001000>, /* ap 40 */
|
|
<0x00086000 0x00086000 0x001000>, /* ap 41 */
|
|
<0x00087000 0x00087000 0x001000>, /* ap 42 */
|
|
<0x00088000 0x00088000 0x001000>, /* ap 43 */
|
|
<0x00089000 0x00089000 0x001000>, /* ap 44 */
|
|
<0x00051000 0x00051000 0x001000>, /* ap 45 */
|
|
<0x00052000 0x00052000 0x001000>, /* ap 46 */
|
|
<0x00098000 0x00098000 0x001000>, /* ap 47 */
|
|
<0x00099000 0x00099000 0x001000>, /* ap 48 */
|
|
<0x0009a000 0x0009a000 0x001000>, /* ap 49 */
|
|
<0x0009b000 0x0009b000 0x001000>, /* ap 50 */
|
|
<0x0009c000 0x0009c000 0x001000>, /* ap 51 */
|
|
<0x0009d000 0x0009d000 0x001000>, /* ap 52 */
|
|
<0x00068000 0x00068000 0x001000>, /* ap 53 */
|
|
<0x00069000 0x00069000 0x001000>, /* ap 54 */
|
|
<0x00090000 0x00090000 0x002000>, /* ap 55 */
|
|
<0x00092000 0x00092000 0x001000>, /* ap 56 */
|
|
<0x000a4000 0x000a4000 0x001000>, /* ap 57 */
|
|
<0x000a6000 0x000a6000 0x001000>, /* ap 58 */
|
|
<0x000a8000 0x000a8000 0x004000>, /* ap 59 */
|
|
<0x000ac000 0x000ac000 0x001000>, /* ap 60 */
|
|
<0x000ad000 0x000ad000 0x001000>, /* ap 61 */
|
|
<0x000ae000 0x000ae000 0x001000>, /* ap 62 */
|
|
<0x00066000 0x00066000 0x001000>, /* ap 63 */
|
|
<0x00067000 0x00067000 0x001000>, /* ap 64 */
|
|
<0x000b4000 0x000b4000 0x001000>, /* ap 65 */
|
|
<0x000b5000 0x000b5000 0x001000>, /* ap 66 */
|
|
<0x000b8000 0x000b8000 0x001000>, /* ap 67 */
|
|
<0x000b9000 0x000b9000 0x001000>, /* ap 68 */
|
|
<0x000ba000 0x000ba000 0x001000>, /* ap 69 */
|
|
<0x000bb000 0x000bb000 0x001000>, /* ap 70 */
|
|
<0x000d1000 0x000d1000 0x001000>, /* ap 71 */
|
|
<0x000d2000 0x000d2000 0x001000>, /* ap 72 */
|
|
<0x000d5000 0x000d5000 0x001000>, /* ap 73 */
|
|
<0x000d6000 0x000d6000 0x001000>, /* ap 74 */
|
|
<0x000a2000 0x000a2000 0x001000>, /* ap 75 */
|
|
<0x000a3000 0x000a3000 0x001000>, /* ap 76 */
|
|
<0x00001400 0x00001400 0x000400>, /* ap 77 */
|
|
<0x00001800 0x00001800 0x000400>, /* ap 78 */
|
|
<0x00001c00 0x00001c00 0x000400>, /* ap 79 */
|
|
<0x000a5000 0x000a5000 0x001000>, /* ap 80 */
|
|
<0x0007a000 0x0007a000 0x001000>, /* ap 81 */
|
|
<0x0007b000 0x0007b000 0x001000>, /* ap 82 */
|
|
<0x0007c000 0x0007c000 0x001000>, /* ap 83 */
|
|
<0x0007d000 0x0007d000 0x001000>; /* ap 84 */
|
|
|
|
target-module@20000 { /* 0x48020000, ap 3 04.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x20050 0x4>,
|
|
<0x20054 0x4>,
|
|
<0x20058 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x20000 0x1000>;
|
|
|
|
uart3: serial@0 {
|
|
compatible = "ti,dra742-uart", "ti,omap4-uart";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <48000000>;
|
|
status = "disabled";
|
|
dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
};
|
|
|
|
target-module@32000 { /* 0x48032000, ap 5 3e.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
ti,hwmods = "timer2";
|
|
reg = <0x32000 0x4>,
|
|
<0x32010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x32000 0x1000>;
|
|
|
|
timer2: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@34000 { /* 0x48034000, ap 7 46.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
ti,hwmods = "timer3";
|
|
reg = <0x34000 0x4>,
|
|
<0x34010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x34000 0x1000>;
|
|
|
|
timer3: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@36000 { /* 0x48036000, ap 9 4e.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
ti,hwmods = "timer4";
|
|
reg = <0x36000 0x4>,
|
|
<0x36010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x36000 0x1000>;
|
|
|
|
timer4: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
reg = <0x3e000 0x4>,
|
|
<0x3e010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x3e000 0x1000>;
|
|
|
|
timer9: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x51000 0x4>,
|
|
<0x51010 0x4>,
|
|
<0x51114 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
|
|
<&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
|
|
clock-names = "fck", "dbclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x51000 0x1000>;
|
|
|
|
gpio7: gpio@0 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
target-module@53000 { /* 0x48053000, ap 35 36.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x53000 0x4>,
|
|
<0x53010 0x4>,
|
|
<0x53114 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
|
|
<&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
|
|
clock-names = "fck", "dbclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x53000 0x1000>;
|
|
|
|
gpio8: gpio@0 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
target-module@55000 { /* 0x48055000, ap 13 0e.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x55000 0x4>,
|
|
<0x55010 0x4>,
|
|
<0x55114 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
|
|
<&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
|
|
clock-names = "fck", "dbclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x55000 0x1000>;
|
|
|
|
gpio2: gpio@0 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
target-module@57000 { /* 0x48057000, ap 15 06.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x57000 0x4>,
|
|
<0x57010 0x4>,
|
|
<0x57114 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
|
|
<&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
|
|
clock-names = "fck", "dbclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x57000 0x1000>;
|
|
|
|
gpio3: gpio@0 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
target-module@59000 { /* 0x48059000, ap 17 16.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x59000 0x4>,
|
|
<0x59010 0x4>,
|
|
<0x59114 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
|
|
<&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
|
|
clock-names = "fck", "dbclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x59000 0x1000>;
|
|
|
|
gpio4: gpio@0 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x5b000 0x4>,
|
|
<0x5b010 0x4>,
|
|
<0x5b114 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
|
|
<&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
|
|
clock-names = "fck", "dbclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x5b000 0x1000>;
|
|
|
|
gpio5: gpio@0 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x5d000 0x4>,
|
|
<0x5d010 0x4>,
|
|
<0x5d114 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
|
|
<&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
|
|
clock-names = "fck", "dbclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x5d000 0x1000>;
|
|
|
|
gpio6: gpio@0 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
target-module@60000 { /* 0x48060000, ap 23 32.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x60000 0x8>,
|
|
<0x60010 0x8>,
|
|
<0x60090 0x8>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x60000 0x1000>;
|
|
|
|
i2c3: i2c@0 {
|
|
compatible = "ti,omap4-i2c";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@66000 { /* 0x48066000, ap 63 14.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x66050 0x4>,
|
|
<0x66054 0x4>,
|
|
<0x66058 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x66000 0x1000>;
|
|
|
|
uart5: serial@0 {
|
|
compatible = "ti,dra742-uart", "ti,omap4-uart";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <48000000>;
|
|
status = "disabled";
|
|
dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
};
|
|
|
|
target-module@68000 { /* 0x48068000, ap 53 1c.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x68050 0x4>,
|
|
<0x68054 0x4>,
|
|
<0x68058 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): ipu_pwrdm, ipu_clkdm */
|
|
clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x68000 0x1000>;
|
|
|
|
uart6: serial@0 {
|
|
compatible = "ti,dra742-uart", "ti,omap4-uart";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <48000000>;
|
|
status = "disabled";
|
|
dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
};
|
|
|
|
target-module@6a000 { /* 0x4806a000, ap 24 24.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x6a050 0x4>,
|
|
<0x6a054 0x4>,
|
|
<0x6a058 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x6a000 0x1000>;
|
|
|
|
uart1: serial@0 {
|
|
compatible = "ti,dra742-uart", "ti,omap4-uart";
|
|
reg = <0x0 0x100>;
|
|
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <48000000>;
|
|
status = "disabled";
|
|
dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
};
|
|
|
|
target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x6c050 0x4>,
|
|
<0x6c054 0x4>,
|
|
<0x6c058 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x6c000 0x1000>;
|
|
|
|
uart2: serial@0 {
|
|
compatible = "ti,dra742-uart", "ti,omap4-uart";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <48000000>;
|
|
status = "disabled";
|
|
dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
};
|
|
|
|
target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x6e050 0x4>,
|
|
<0x6e054 0x4>,
|
|
<0x6e058 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x6e000 0x1000>;
|
|
|
|
uart4: serial@0 {
|
|
compatible = "ti,dra742-uart", "ti,omap4-uart";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <48000000>;
|
|
status = "disabled";
|
|
dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
};
|
|
|
|
target-module@70000 { /* 0x48070000, ap 30 22.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x70000 0x8>,
|
|
<0x70010 0x8>,
|
|
<0x70090 0x8>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x70000 0x1000>;
|
|
|
|
i2c1: i2c@0 {
|
|
compatible = "ti,omap4-i2c";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@72000 { /* 0x48072000, ap 32 2a.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x72000 0x8>,
|
|
<0x72010 0x8>,
|
|
<0x72090 0x8>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x72000 0x1000>;
|
|
|
|
i2c2: i2c@0 {
|
|
compatible = "ti,omap4-i2c";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@78000 { /* 0x48078000, ap 39 0a.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x78000 0x4>,
|
|
<0x78010 0x4>,
|
|
<0x78014 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x78000 0x1000>;
|
|
|
|
elm: elm@0 {
|
|
compatible = "ti,am3352-elm";
|
|
reg = <0x0 0xfc0>; /* device IO registers */
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x7a000 0x8>,
|
|
<0x7a010 0x8>,
|
|
<0x7a090 0x8>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x7a000 0x1000>;
|
|
|
|
i2c4: i2c@0 {
|
|
compatible = "ti,omap4-i2c";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x7c000 0x8>,
|
|
<0x7c010 0x8>,
|
|
<0x7c090 0x8>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): ipu_pwrdm, ipu_clkdm */
|
|
clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x7c000 0x1000>;
|
|
|
|
i2c5: i2c@0 {
|
|
compatible = "ti,omap4-i2c";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@86000 { /* 0x48086000, ap 41 5e.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
reg = <0x86000 0x4>,
|
|
<0x86010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x86000 0x1000>;
|
|
|
|
timer10: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@88000 { /* 0x48088000, ap 43 66.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
reg = <0x88000 0x4>,
|
|
<0x88010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x88000 0x1000>;
|
|
|
|
timer11: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@90000 { /* 0x48090000, ap 55 12.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x91fe0 0x4>,
|
|
<0x91fe4 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>;
|
|
/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
|
|
clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x90000 0x2000>;
|
|
|
|
rng: rng@0 {
|
|
compatible = "ti,omap4-rng";
|
|
reg = <0x0 0x2000>;
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&l3_iclk_div>;
|
|
clock-names = "fck";
|
|
};
|
|
};
|
|
|
|
target-module@98000 { /* 0x48098000, ap 47 08.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x98000 0x4>,
|
|
<0x98010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x98000 0x1000>;
|
|
|
|
mcspi1: spi@0 {
|
|
compatible = "ti,omap4-mcspi";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,spi-num-cs = <4>;
|
|
dmas = <&sdma_xbar 35>,
|
|
<&sdma_xbar 36>,
|
|
<&sdma_xbar 37>,
|
|
<&sdma_xbar 38>,
|
|
<&sdma_xbar 39>,
|
|
<&sdma_xbar 40>,
|
|
<&sdma_xbar 41>,
|
|
<&sdma_xbar 42>;
|
|
dma-names = "tx0", "rx0", "tx1", "rx1",
|
|
"tx2", "rx2", "tx3", "rx3";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x9a000 0x4>,
|
|
<0x9a010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x9a000 0x1000>;
|
|
|
|
mcspi2: spi@0 {
|
|
compatible = "ti,omap4-mcspi";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,spi-num-cs = <2>;
|
|
dmas = <&sdma_xbar 43>,
|
|
<&sdma_xbar 44>,
|
|
<&sdma_xbar 45>,
|
|
<&sdma_xbar 46>;
|
|
dma-names = "tx0", "rx0", "tx1", "rx1";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@9c000 { /* 0x4809c000, ap 51 38.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x9c000 0x4>,
|
|
<0x9c010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l3init_pwrdm, l3init_clkdm */
|
|
clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x9c000 0x1000>;
|
|
|
|
mmc1: mmc@0 {
|
|
compatible = "ti,dra7-sdhci";
|
|
reg = <0x0 0x400>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
pbias-supply = <&pbias_mmc_reg>;
|
|
max-frequency = <192000000>;
|
|
mmc-ddr-1_8v;
|
|
mmc-ddr-3_3v;
|
|
};
|
|
};
|
|
|
|
target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xa2000 0x1000>;
|
|
};
|
|
|
|
target-module@a4000 { /* 0x480a4000, ap 57 42.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00000000 0x000a4000 0x00001000>,
|
|
<0x00001000 0x000a5000 0x00001000>;
|
|
};
|
|
|
|
des_target: target-module@a5000 { /* 0x480a5000 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0xa5030 0x4>,
|
|
<0xa5034 0x4>,
|
|
<0xa5038 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
|
|
clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0xa5000 0x00001000>;
|
|
|
|
des: des@0 {
|
|
compatible = "ti,omap4-des";
|
|
reg = <0 0xa0>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&l3_iclk_div>;
|
|
clock-names = "fck";
|
|
};
|
|
};
|
|
|
|
target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xa8000 0x4000>;
|
|
};
|
|
|
|
target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0xad000 0x4>,
|
|
<0xad010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xad000 0x1000>;
|
|
|
|
mmc3: mmc@0 {
|
|
compatible = "ti,dra7-sdhci";
|
|
reg = <0x0 0x400>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
/* Errata i887 limits max-frequency of MMC3 to 64 MHz */
|
|
max-frequency = <64000000>;
|
|
/* SDMA is not supported */
|
|
sdhci-caps-mask = <0x0 0x400000>;
|
|
};
|
|
};
|
|
|
|
target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0xb2000 0x4>,
|
|
<0xb2014 0x4>,
|
|
<0xb2018 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,syss-mask = <1>;
|
|
ti,no-reset-on-init;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xb2000 0x1000>;
|
|
|
|
hdqw1w: 1w@0 {
|
|
compatible = "ti,omap3-1w";
|
|
reg = <0x0 0x1000>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@b4000 { /* 0x480b4000, ap 65 40.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0xb4000 0x4>,
|
|
<0xb4010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l3init_pwrdm, l3init_clkdm */
|
|
clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xb4000 0x1000>;
|
|
|
|
mmc2: mmc@0 {
|
|
compatible = "ti,dra7-sdhci";
|
|
reg = <0x0 0x400>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
max-frequency = <192000000>;
|
|
/* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
|
|
sdhci-caps-mask = <0x7 0x0>;
|
|
mmc-hs200-1_8v;
|
|
mmc-ddr-1_8v;
|
|
mmc-ddr-3_3v;
|
|
};
|
|
};
|
|
|
|
target-module@b8000 { /* 0x480b8000, ap 67 48.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0xb8000 0x4>,
|
|
<0xb8010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xb8000 0x1000>;
|
|
|
|
mcspi3: spi@0 {
|
|
compatible = "ti,omap4-mcspi";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,spi-num-cs = <2>;
|
|
dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
|
|
dma-names = "tx0", "rx0";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0xba000 0x4>,
|
|
<0xba010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xba000 0x1000>;
|
|
|
|
mcspi4: spi@0 {
|
|
compatible = "ti,omap4-mcspi";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,spi-num-cs = <1>;
|
|
dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
|
|
dma-names = "tx0", "rx0";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0xd1000 0x4>,
|
|
<0xd1010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
|
|
clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xd1000 0x1000>;
|
|
|
|
mmc4: mmc@0 {
|
|
compatible = "ti,dra7-sdhci";
|
|
reg = <0x0 0x400>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
max-frequency = <192000000>;
|
|
/* SDMA is not supported */
|
|
sdhci-caps-mask = <0x0 0x400000>;
|
|
};
|
|
};
|
|
|
|
target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xd5000 0x1000>;
|
|
};
|
|
};
|
|
|
|
segment@200000 { /* 0x48200000 */
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
};
|
|
|
|
&l4_per2 { /* 0x48400000 */
|
|
compatible = "ti,dra7-l4-per2", "simple-bus";
|
|
reg = <0x48400000 0x800>,
|
|
<0x48400800 0x800>,
|
|
<0x48401000 0x400>,
|
|
<0x48401400 0x400>,
|
|
<0x48401800 0x400>;
|
|
reg-names = "ap", "la", "ia0", "ia1", "ia2";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */
|
|
<0x45800000 0x45800000 0x400000>, /* L3 data port */
|
|
<0x45c00000 0x45c00000 0x400000>, /* L3 data port */
|
|
<0x46000000 0x46000000 0x400000>, /* L3 data port */
|
|
<0x48436000 0x48436000 0x400000>, /* L3 data port */
|
|
<0x4843a000 0x4843a000 0x400000>, /* L3 data port */
|
|
<0x4844c000 0x4844c000 0x400000>, /* L3 data port */
|
|
<0x48450000 0x48450000 0x400000>, /* L3 data port */
|
|
<0x48454000 0x48454000 0x400000>; /* L3 data port */
|
|
|
|
segment@0 { /* 0x48400000 */
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
|
|
<0x00001000 0x00001000 0x000400>, /* ap 1 */
|
|
<0x00000800 0x00000800 0x000800>, /* ap 2 */
|
|
<0x00084000 0x00084000 0x004000>, /* ap 3 */
|
|
<0x00001400 0x00001400 0x000400>, /* ap 4 */
|
|
<0x00001800 0x00001800 0x000400>, /* ap 5 */
|
|
<0x00088000 0x00088000 0x001000>, /* ap 6 */
|
|
<0x0002c000 0x0002c000 0x001000>, /* ap 7 */
|
|
<0x0002d000 0x0002d000 0x001000>, /* ap 8 */
|
|
<0x00060000 0x00060000 0x002000>, /* ap 9 */
|
|
<0x00062000 0x00062000 0x001000>, /* ap 10 */
|
|
<0x00064000 0x00064000 0x002000>, /* ap 11 */
|
|
<0x00066000 0x00066000 0x001000>, /* ap 12 */
|
|
<0x00068000 0x00068000 0x002000>, /* ap 13 */
|
|
<0x0006a000 0x0006a000 0x001000>, /* ap 14 */
|
|
<0x0006c000 0x0006c000 0x002000>, /* ap 15 */
|
|
<0x0006e000 0x0006e000 0x001000>, /* ap 16 */
|
|
<0x00036000 0x00036000 0x001000>, /* ap 17 */
|
|
<0x00037000 0x00037000 0x001000>, /* ap 18 */
|
|
<0x00070000 0x00070000 0x002000>, /* ap 19 */
|
|
<0x00072000 0x00072000 0x001000>, /* ap 20 */
|
|
<0x0003a000 0x0003a000 0x001000>, /* ap 21 */
|
|
<0x0003b000 0x0003b000 0x001000>, /* ap 22 */
|
|
<0x0003c000 0x0003c000 0x001000>, /* ap 23 */
|
|
<0x0003d000 0x0003d000 0x001000>, /* ap 24 */
|
|
<0x0003e000 0x0003e000 0x001000>, /* ap 25 */
|
|
<0x0003f000 0x0003f000 0x001000>, /* ap 26 */
|
|
<0x00040000 0x00040000 0x001000>, /* ap 27 */
|
|
<0x00041000 0x00041000 0x001000>, /* ap 28 */
|
|
<0x00042000 0x00042000 0x001000>, /* ap 29 */
|
|
<0x00043000 0x00043000 0x001000>, /* ap 30 */
|
|
<0x00080000 0x00080000 0x002000>, /* ap 31 */
|
|
<0x00082000 0x00082000 0x001000>, /* ap 32 */
|
|
<0x0004a000 0x0004a000 0x001000>, /* ap 33 */
|
|
<0x0004b000 0x0004b000 0x001000>, /* ap 34 */
|
|
<0x00074000 0x00074000 0x002000>, /* ap 35 */
|
|
<0x00076000 0x00076000 0x001000>, /* ap 36 */
|
|
<0x00050000 0x00050000 0x001000>, /* ap 37 */
|
|
<0x00051000 0x00051000 0x001000>, /* ap 38 */
|
|
<0x00078000 0x00078000 0x002000>, /* ap 39 */
|
|
<0x0007a000 0x0007a000 0x001000>, /* ap 40 */
|
|
<0x00054000 0x00054000 0x001000>, /* ap 41 */
|
|
<0x00055000 0x00055000 0x001000>, /* ap 42 */
|
|
<0x0007c000 0x0007c000 0x002000>, /* ap 43 */
|
|
<0x0007e000 0x0007e000 0x001000>, /* ap 44 */
|
|
<0x0004c000 0x0004c000 0x001000>, /* ap 45 */
|
|
<0x0004d000 0x0004d000 0x001000>, /* ap 46 */
|
|
<0x00020000 0x00020000 0x001000>, /* ap 47 */
|
|
<0x00021000 0x00021000 0x001000>, /* ap 48 */
|
|
<0x00022000 0x00022000 0x001000>, /* ap 49 */
|
|
<0x00023000 0x00023000 0x001000>, /* ap 50 */
|
|
<0x00024000 0x00024000 0x001000>, /* ap 51 */
|
|
<0x00025000 0x00025000 0x001000>, /* ap 52 */
|
|
<0x00046000 0x00046000 0x001000>, /* ap 53 */
|
|
<0x00047000 0x00047000 0x001000>, /* ap 54 */
|
|
<0x00048000 0x00048000 0x001000>, /* ap 55 */
|
|
<0x00049000 0x00049000 0x001000>, /* ap 56 */
|
|
<0x00058000 0x00058000 0x002000>, /* ap 57 */
|
|
<0x0005a000 0x0005a000 0x001000>, /* ap 58 */
|
|
<0x0005b000 0x0005b000 0x001000>, /* ap 59 */
|
|
<0x0005c000 0x0005c000 0x001000>, /* ap 60 */
|
|
<0x0005d000 0x0005d000 0x001000>, /* ap 61 */
|
|
<0x0005e000 0x0005e000 0x001000>, /* ap 62 */
|
|
<0x45800000 0x45800000 0x400000>, /* L3 data port */
|
|
<0x45c00000 0x45c00000 0x400000>, /* L3 data port */
|
|
<0x46000000 0x46000000 0x400000>, /* L3 data port */
|
|
<0x48436000 0x48436000 0x400000>, /* L3 data port */
|
|
<0x4843a000 0x4843a000 0x400000>, /* L3 data port */
|
|
<0x4844c000 0x4844c000 0x400000>, /* L3 data port */
|
|
<0x48450000 0x48450000 0x400000>, /* L3 data port */
|
|
<0x48454000 0x48454000 0x400000>; /* L3 data port */
|
|
|
|
target-module@20000 { /* 0x48420000, ap 47 02.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x20050 0x4>,
|
|
<0x20054 0x4>,
|
|
<0x20058 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x20000 0x1000>;
|
|
|
|
uart7: serial@0 {
|
|
compatible = "ti,dra742-uart", "ti,omap4-uart";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@22000 { /* 0x48422000, ap 49 0a.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x22050 0x4>,
|
|
<0x22054 0x4>,
|
|
<0x22058 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x22000 0x1000>;
|
|
|
|
uart8: serial@0 {
|
|
compatible = "ti,dra742-uart", "ti,omap4-uart";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@24000 { /* 0x48424000, ap 51 12.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x24050 0x4>,
|
|
<0x24054 0x4>,
|
|
<0x24058 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x24000 0x1000>;
|
|
|
|
uart9: serial@0 {
|
|
compatible = "ti,dra742-uart", "ti,omap4-uart";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@2c000 { /* 0x4842c000, ap 7 18.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x2c000 0x1000>;
|
|
};
|
|
|
|
target-module@36000 { /* 0x48436000, ap 17 06.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x36000 0x1000>;
|
|
};
|
|
|
|
target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x3a000 0x1000>;
|
|
};
|
|
|
|
atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x3c000 0x4>;
|
|
reg-names = "rev";
|
|
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x3c000 0x1000>;
|
|
|
|
atl: atl@0 {
|
|
compatible = "ti,dra7-atl";
|
|
reg = <0x0 0x3ff>;
|
|
ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
|
|
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
|
|
clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
|
|
clock-names = "fck";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x3e000 0x4>,
|
|
<0x3e004 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x3e000 0x1000>;
|
|
|
|
epwmss0: epwmss@0 {
|
|
compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
|
|
reg = <0x0 0x30>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "disabled";
|
|
ranges = <0 0 0x1000>;
|
|
|
|
ecap0: ecap@100 {
|
|
compatible = "ti,dra746-ecap",
|
|
"ti,am3352-ecap";
|
|
#pwm-cells = <3>;
|
|
reg = <0x100 0x80>;
|
|
clocks = <&l4_root_clk_div>;
|
|
clock-names = "fck";
|
|
status = "disabled";
|
|
};
|
|
|
|
ehrpwm0: pwm@200 {
|
|
compatible = "ti,dra746-ehrpwm",
|
|
"ti,am3352-ehrpwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x200 0x80>;
|
|
clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
|
|
clock-names = "tbclk", "fck";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
target-module@40000 { /* 0x48440000, ap 27 38.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x40000 0x4>,
|
|
<0x40004 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x40000 0x1000>;
|
|
|
|
epwmss1: epwmss@0 {
|
|
compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
|
|
reg = <0x0 0x30>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "disabled";
|
|
ranges = <0 0 0x1000>;
|
|
|
|
ecap1: ecap@100 {
|
|
compatible = "ti,dra746-ecap",
|
|
"ti,am3352-ecap";
|
|
#pwm-cells = <3>;
|
|
reg = <0x100 0x80>;
|
|
clocks = <&l4_root_clk_div>;
|
|
clock-names = "fck";
|
|
status = "disabled";
|
|
};
|
|
|
|
ehrpwm1: pwm@200 {
|
|
compatible = "ti,dra746-ehrpwm",
|
|
"ti,am3352-ehrpwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x200 0x80>;
|
|
clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
|
|
clock-names = "tbclk", "fck";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
target-module@42000 { /* 0x48442000, ap 29 20.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x42000 0x4>,
|
|
<0x42004 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x42000 0x1000>;
|
|
|
|
epwmss2: epwmss@0 {
|
|
compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
|
|
reg = <0x0 0x30>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
status = "disabled";
|
|
ranges = <0 0 0x1000>;
|
|
|
|
ecap2: ecap@100 {
|
|
compatible = "ti,dra746-ecap",
|
|
"ti,am3352-ecap";
|
|
#pwm-cells = <3>;
|
|
reg = <0x100 0x80>;
|
|
clocks = <&l4_root_clk_div>;
|
|
clock-names = "fck";
|
|
status = "disabled";
|
|
};
|
|
|
|
ehrpwm2: pwm@200 {
|
|
compatible = "ti,dra746-ehrpwm",
|
|
"ti,am3352-ehrpwm";
|
|
#pwm-cells = <3>;
|
|
reg = <0x200 0x80>;
|
|
clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
|
|
clock-names = "tbclk", "fck";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
target-module@46000 { /* 0x48446000, ap 53 40.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x46000 0x1000>;
|
|
};
|
|
|
|
target-module@48000 { /* 0x48448000, ap 55 48.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x48000 0x1000>;
|
|
};
|
|
|
|
target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x4a000 0x1000>;
|
|
};
|
|
|
|
target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x4c000 0x1000>;
|
|
};
|
|
|
|
target-module@50000 { /* 0x48450000, ap 37 24.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x50000 0x1000>;
|
|
};
|
|
|
|
target-module@54000 { /* 0x48454000, ap 41 2c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x54000 0x1000>;
|
|
};
|
|
|
|
target-module@58000 { /* 0x48458000, ap 57 28.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x58000 0x2000>;
|
|
};
|
|
|
|
target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x5b000 0x1000>;
|
|
};
|
|
|
|
target-module@5d000 { /* 0x4845d000, ap 61 22.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x5d000 0x1000>;
|
|
};
|
|
|
|
target-module@60000 { /* 0x48460000, ap 9 0e.0 */
|
|
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
|
|
reg = <0x60000 0x4>,
|
|
<0x60004 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): ipu_pwrdm, ipu_clkdm */
|
|
clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
|
|
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
|
|
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
|
|
clock-names = "fck", "ahclkx", "ahclkr";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x60000 0x2000>,
|
|
<0x45800000 0x45800000 0x400000>;
|
|
|
|
mcasp1: mcasp@0 {
|
|
compatible = "ti,dra7-mcasp-audio";
|
|
reg = <0x0 0x2000>,
|
|
<0x45800000 0x1000>; /* L3 data port */
|
|
reg-names = "mpu","dat";
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tx", "rx";
|
|
dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
|
|
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
|
|
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
|
|
clock-names = "fck", "ahclkx", "ahclkr";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@64000 { /* 0x48464000, ap 11 1e.0 */
|
|
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
|
|
reg = <0x64000 0x4>,
|
|
<0x64004 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
|
|
clock-names = "fck", "ahclkx", "ahclkr";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x64000 0x2000>,
|
|
<0x45c00000 0x45c00000 0x400000>;
|
|
|
|
mcasp2: mcasp@0 {
|
|
compatible = "ti,dra7-mcasp-audio";
|
|
reg = <0x0 0x2000>,
|
|
<0x45c00000 0x1000>; /* L3 data port */
|
|
reg-names = "mpu","dat";
|
|
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tx", "rx";
|
|
dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
|
|
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
|
|
clock-names = "fck", "ahclkx", "ahclkr";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@68000 { /* 0x48468000, ap 13 26.0 */
|
|
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
|
|
reg = <0x68000 0x4>,
|
|
<0x68004 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
|
|
clock-names = "fck", "ahclkx";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x68000 0x2000>,
|
|
<0x46000000 0x46000000 0x400000>;
|
|
|
|
mcasp3: mcasp@0 {
|
|
compatible = "ti,dra7-mcasp-audio";
|
|
reg = <0x0 0x2000>,
|
|
<0x46000000 0x1000>; /* L3 data port */
|
|
reg-names = "mpu","dat";
|
|
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tx", "rx";
|
|
dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
|
|
clock-names = "fck", "ahclkx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
|
|
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
|
|
reg = <0x6c000 0x4>,
|
|
<0x6c004 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
|
|
clock-names = "fck", "ahclkx";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x6c000 0x2000>,
|
|
<0x48436000 0x48436000 0x400000>;
|
|
|
|
mcasp4: mcasp@0 {
|
|
compatible = "ti,dra7-mcasp-audio";
|
|
reg = <0x0 0x2000>,
|
|
<0x48436000 0x1000>; /* L3 data port */
|
|
reg-names = "mpu","dat";
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tx", "rx";
|
|
dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
|
|
clock-names = "fck", "ahclkx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@70000 { /* 0x48470000, ap 19 36.0 */
|
|
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
|
|
reg = <0x70000 0x4>,
|
|
<0x70004 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
|
|
clock-names = "fck", "ahclkx";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x70000 0x2000>,
|
|
<0x4843a000 0x4843a000 0x400000>;
|
|
|
|
mcasp5: mcasp@0 {
|
|
compatible = "ti,dra7-mcasp-audio";
|
|
reg = <0x0 0x2000>,
|
|
<0x4843a000 0x1000>; /* L3 data port */
|
|
reg-names = "mpu","dat";
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tx", "rx";
|
|
dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
|
|
clock-names = "fck", "ahclkx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@74000 { /* 0x48474000, ap 35 14.0 */
|
|
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
|
|
reg = <0x74000 0x4>,
|
|
<0x74004 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
|
|
clock-names = "fck", "ahclkx";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x74000 0x2000>,
|
|
<0x4844c000 0x4844c000 0x400000>;
|
|
|
|
mcasp6: mcasp@0 {
|
|
compatible = "ti,dra7-mcasp-audio";
|
|
reg = <0x0 0x2000>,
|
|
<0x4844c000 0x1000>; /* L3 data port */
|
|
reg-names = "mpu","dat";
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tx", "rx";
|
|
dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
|
|
clock-names = "fck", "ahclkx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@78000 { /* 0x48478000, ap 39 0c.0 */
|
|
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
|
|
reg = <0x78000 0x4>,
|
|
<0x78004 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
|
|
clock-names = "fck", "ahclkx";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x78000 0x2000>,
|
|
<0x48450000 0x48450000 0x400000>;
|
|
|
|
mcasp7: mcasp@0 {
|
|
compatible = "ti,dra7-mcasp-audio";
|
|
reg = <0x0 0x2000>,
|
|
<0x48450000 0x1000>; /* L3 data port */
|
|
reg-names = "mpu","dat";
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tx", "rx";
|
|
dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
|
|
clock-names = "fck", "ahclkx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
|
|
compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
|
|
reg = <0x7c000 0x4>,
|
|
<0x7c004 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
|
|
clock-names = "fck", "ahclkx";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x7c000 0x2000>,
|
|
<0x48454000 0x48454000 0x400000>;
|
|
|
|
mcasp8: mcasp@0 {
|
|
compatible = "ti,dra7-mcasp-audio";
|
|
reg = <0x0 0x2000>,
|
|
<0x48454000 0x1000>; /* L3 data port */
|
|
reg-names = "mpu","dat";
|
|
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tx", "rx";
|
|
dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
|
|
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
|
|
clock-names = "fck", "ahclkx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@80000 { /* 0x48480000, ap 31 16.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x80020 0x4>;
|
|
reg-names = "rev";
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x80000 0x2000>;
|
|
|
|
dcan2: can@0 {
|
|
compatible = "ti,dra7-d_can";
|
|
reg = <0x0 0x2000>;
|
|
syscon-raminit = <&scm_conf 0x558 1>;
|
|
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&sys_clkin1>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@84000 { /* 0x48484000, ap 3 10.0 */
|
|
compatible = "ti,sysc-omap4-simple", "ti,sysc";
|
|
reg = <0x85200 0x4>,
|
|
<0x85208 0x4>,
|
|
<0x85204 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <0>;
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>;
|
|
ti,syss-mask = <1>;
|
|
clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x84000 0x4000>;
|
|
/*
|
|
* Do not allow gating of cpsw clock as workaround
|
|
* for errata i877. Keeping internal clock disabled
|
|
* causes the device switching characteristics
|
|
* to degrade over time and eventually fail to meet
|
|
* the data manual delay time/skew specs.
|
|
*/
|
|
ti,no-idle;
|
|
|
|
mac: ethernet@0 {
|
|
compatible = "ti,dra7-cpsw","ti,cpsw";
|
|
clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
|
|
clock-names = "fck", "cpts";
|
|
cpdma_channels = <8>;
|
|
ale_entries = <1024>;
|
|
bd_ram_size = <0x2000>;
|
|
mac_control = <0x20>;
|
|
slaves = <2>;
|
|
active_slave = <0>;
|
|
cpts_clock_mult = <0x784CFE14>;
|
|
cpts_clock_shift = <29>;
|
|
reg = <0x0 0x1000
|
|
0x1200 0x2e00>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
/*
|
|
* rx_thresh_pend
|
|
* rx_pend
|
|
* tx_pend
|
|
* misc_pend
|
|
*/
|
|
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
|
|
ranges = <0 0 0x4000>;
|
|
syscon = <&scm_conf>;
|
|
status = "disabled";
|
|
|
|
davinci_mdio: mdio@1000 {
|
|
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
|
clocks = <&gmac_main_clk>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
bus_freq = <1000000>;
|
|
reg = <0x1000 0x100>;
|
|
};
|
|
|
|
cpsw_emac0: slave@200 {
|
|
/* Filled in by U-Boot */
|
|
mac-address = [ 00 00 00 00 00 00 ];
|
|
phys = <&phy_gmii_sel 1>;
|
|
};
|
|
|
|
cpsw_emac1: slave@300 {
|
|
/* Filled in by U-Boot */
|
|
mac-address = [ 00 00 00 00 00 00 ];
|
|
phys = <&phy_gmii_sel 2>;
|
|
};
|
|
};
|
|
|
|
mac_sw: switch@0 {
|
|
compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
|
|
reg = <0x0 0x4000>;
|
|
ranges = <0 0 0x4000>;
|
|
clocks = <&gmac_main_clk>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
syscon = <&scm_conf>;
|
|
status = "disabled";
|
|
|
|
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "rx_thresh", "rx", "tx", "misc";
|
|
|
|
ethernet-ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpsw_port1: port@1 {
|
|
reg = <1>;
|
|
label = "port1";
|
|
mac-address = [ 00 00 00 00 00 00 ];
|
|
phys = <&phy_gmii_sel 1>;
|
|
};
|
|
|
|
cpsw_port2: port@2 {
|
|
reg = <2>;
|
|
label = "port2";
|
|
mac-address = [ 00 00 00 00 00 00 ];
|
|
phys = <&phy_gmii_sel 2>;
|
|
};
|
|
};
|
|
|
|
davinci_mdio_sw: mdio@1000 {
|
|
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
|
clocks = <&gmac_main_clk>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
bus_freq = <1000000>;
|
|
reg = <0x1000 0x100>;
|
|
};
|
|
|
|
cpts {
|
|
clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
|
|
clock-names = "cpts";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&l4_per3 { /* 0x48800000 */
|
|
compatible = "ti,dra7-l4-per3", "simple-bus";
|
|
reg = <0x48800000 0x800>,
|
|
<0x48800800 0x800>,
|
|
<0x48801000 0x400>,
|
|
<0x48801400 0x400>,
|
|
<0x48801800 0x400>;
|
|
reg-names = "ap", "la", "ia0", "ia1", "ia2";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */
|
|
|
|
segment@0 { /* 0x48800000 */
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
|
|
<0x00000800 0x00000800 0x000800>, /* ap 1 */
|
|
<0x00001000 0x00001000 0x000400>, /* ap 2 */
|
|
<0x00001400 0x00001400 0x000400>, /* ap 3 */
|
|
<0x00001800 0x00001800 0x000400>, /* ap 4 */
|
|
<0x00020000 0x00020000 0x001000>, /* ap 5 */
|
|
<0x00021000 0x00021000 0x001000>, /* ap 6 */
|
|
<0x00022000 0x00022000 0x001000>, /* ap 7 */
|
|
<0x00023000 0x00023000 0x001000>, /* ap 8 */
|
|
<0x00024000 0x00024000 0x001000>, /* ap 9 */
|
|
<0x00025000 0x00025000 0x001000>, /* ap 10 */
|
|
<0x00026000 0x00026000 0x001000>, /* ap 11 */
|
|
<0x00027000 0x00027000 0x001000>, /* ap 12 */
|
|
<0x00028000 0x00028000 0x001000>, /* ap 13 */
|
|
<0x00029000 0x00029000 0x001000>, /* ap 14 */
|
|
<0x0002a000 0x0002a000 0x001000>, /* ap 15 */
|
|
<0x0002b000 0x0002b000 0x001000>, /* ap 16 */
|
|
<0x0002c000 0x0002c000 0x001000>, /* ap 17 */
|
|
<0x0002d000 0x0002d000 0x001000>, /* ap 18 */
|
|
<0x0002e000 0x0002e000 0x001000>, /* ap 19 */
|
|
<0x0002f000 0x0002f000 0x001000>, /* ap 20 */
|
|
<0x00170000 0x00170000 0x010000>, /* ap 21 */
|
|
<0x00180000 0x00180000 0x001000>, /* ap 22 */
|
|
<0x00190000 0x00190000 0x010000>, /* ap 23 */
|
|
<0x001a0000 0x001a0000 0x001000>, /* ap 24 */
|
|
<0x001b0000 0x001b0000 0x010000>, /* ap 25 */
|
|
<0x001c0000 0x001c0000 0x001000>, /* ap 26 */
|
|
<0x001d0000 0x001d0000 0x010000>, /* ap 27 */
|
|
<0x001e0000 0x001e0000 0x001000>, /* ap 28 */
|
|
<0x00038000 0x00038000 0x001000>, /* ap 29 */
|
|
<0x00039000 0x00039000 0x001000>, /* ap 30 */
|
|
<0x0005c000 0x0005c000 0x001000>, /* ap 31 */
|
|
<0x0005d000 0x0005d000 0x001000>, /* ap 32 */
|
|
<0x0003a000 0x0003a000 0x001000>, /* ap 33 */
|
|
<0x0003b000 0x0003b000 0x001000>, /* ap 34 */
|
|
<0x0003c000 0x0003c000 0x001000>, /* ap 35 */
|
|
<0x0003d000 0x0003d000 0x001000>, /* ap 36 */
|
|
<0x0003e000 0x0003e000 0x001000>, /* ap 37 */
|
|
<0x0003f000 0x0003f000 0x001000>, /* ap 38 */
|
|
<0x00040000 0x00040000 0x001000>, /* ap 39 */
|
|
<0x00041000 0x00041000 0x001000>, /* ap 40 */
|
|
<0x00042000 0x00042000 0x001000>, /* ap 41 */
|
|
<0x00043000 0x00043000 0x001000>, /* ap 42 */
|
|
<0x00044000 0x00044000 0x001000>, /* ap 43 */
|
|
<0x00045000 0x00045000 0x001000>, /* ap 44 */
|
|
<0x00046000 0x00046000 0x001000>, /* ap 45 */
|
|
<0x00047000 0x00047000 0x001000>, /* ap 46 */
|
|
<0x00048000 0x00048000 0x001000>, /* ap 47 */
|
|
<0x00049000 0x00049000 0x001000>, /* ap 48 */
|
|
<0x0004a000 0x0004a000 0x001000>, /* ap 49 */
|
|
<0x0004b000 0x0004b000 0x001000>, /* ap 50 */
|
|
<0x0004c000 0x0004c000 0x001000>, /* ap 51 */
|
|
<0x0004d000 0x0004d000 0x001000>, /* ap 52 */
|
|
<0x0004e000 0x0004e000 0x001000>, /* ap 53 */
|
|
<0x0004f000 0x0004f000 0x001000>, /* ap 54 */
|
|
<0x00050000 0x00050000 0x001000>, /* ap 55 */
|
|
<0x00051000 0x00051000 0x001000>, /* ap 56 */
|
|
<0x00052000 0x00052000 0x001000>, /* ap 57 */
|
|
<0x00053000 0x00053000 0x001000>, /* ap 58 */
|
|
<0x00054000 0x00054000 0x001000>, /* ap 59 */
|
|
<0x00055000 0x00055000 0x001000>, /* ap 60 */
|
|
<0x00056000 0x00056000 0x001000>, /* ap 61 */
|
|
<0x00057000 0x00057000 0x001000>, /* ap 62 */
|
|
<0x00058000 0x00058000 0x001000>, /* ap 63 */
|
|
<0x00059000 0x00059000 0x001000>, /* ap 64 */
|
|
<0x0005a000 0x0005a000 0x001000>, /* ap 65 */
|
|
<0x0005b000 0x0005b000 0x001000>, /* ap 66 */
|
|
<0x00064000 0x00064000 0x001000>, /* ap 67 */
|
|
<0x00065000 0x00065000 0x001000>, /* ap 68 */
|
|
<0x0005e000 0x0005e000 0x001000>, /* ap 69 */
|
|
<0x0005f000 0x0005f000 0x001000>, /* ap 70 */
|
|
<0x00060000 0x00060000 0x001000>, /* ap 71 */
|
|
<0x00061000 0x00061000 0x001000>, /* ap 72 */
|
|
<0x00062000 0x00062000 0x001000>, /* ap 73 */
|
|
<0x00063000 0x00063000 0x001000>, /* ap 74 */
|
|
<0x00140000 0x00140000 0x020000>, /* ap 75 */
|
|
<0x00160000 0x00160000 0x001000>, /* ap 76 */
|
|
<0x00016000 0x00016000 0x001000>, /* ap 77 */
|
|
<0x00017000 0x00017000 0x001000>, /* ap 78 */
|
|
<0x000c0000 0x000c0000 0x020000>, /* ap 79 */
|
|
<0x000e0000 0x000e0000 0x001000>, /* ap 80 */
|
|
<0x00004000 0x00004000 0x001000>, /* ap 81 */
|
|
<0x00005000 0x00005000 0x001000>, /* ap 82 */
|
|
<0x00080000 0x00080000 0x020000>, /* ap 83 */
|
|
<0x000a0000 0x000a0000 0x001000>, /* ap 84 */
|
|
<0x00100000 0x00100000 0x020000>, /* ap 85 */
|
|
<0x00120000 0x00120000 0x001000>, /* ap 86 */
|
|
<0x00010000 0x00010000 0x001000>, /* ap 87 */
|
|
<0x00011000 0x00011000 0x001000>, /* ap 88 */
|
|
<0x0000a000 0x0000a000 0x001000>, /* ap 89 */
|
|
<0x0000b000 0x0000b000 0x001000>, /* ap 90 */
|
|
<0x0001c000 0x0001c000 0x001000>, /* ap 91 */
|
|
<0x0001d000 0x0001d000 0x001000>, /* ap 92 */
|
|
<0x0001e000 0x0001e000 0x001000>, /* ap 93 */
|
|
<0x0001f000 0x0001f000 0x001000>, /* ap 94 */
|
|
<0x00002000 0x00002000 0x001000>, /* ap 95 */
|
|
<0x00003000 0x00003000 0x001000>; /* ap 96 */
|
|
|
|
target-module@2000 { /* 0x48802000, ap 95 7c.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x2000 0x4>,
|
|
<0x2010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x2000 0x1000>;
|
|
|
|
mailbox13: mailbox@0 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
ti,mbox-num-users = <4>;
|
|
ti,mbox-num-fifos = <12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@4000 { /* 0x48804000, ap 81 20.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x4000 0x1000>;
|
|
};
|
|
|
|
target-module@a000 { /* 0x4880a000, ap 89 18.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xa000 0x1000>;
|
|
};
|
|
|
|
target-module@10000 { /* 0x48810000, ap 87 28.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x10000 0x1000>;
|
|
};
|
|
|
|
target-module@16000 { /* 0x48816000, ap 77 1e.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x16000 0x1000>;
|
|
};
|
|
|
|
target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x1c000 0x1000>;
|
|
};
|
|
|
|
target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x1e000 0x1000>;
|
|
};
|
|
|
|
target-module@20000 { /* 0x48820000, ap 5 08.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
reg = <0x20000 0x4>,
|
|
<0x20010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): ipu_pwrdm, ipu_clkdm */
|
|
clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x20000 0x1000>;
|
|
|
|
timer5: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@22000 { /* 0x48822000, ap 7 24.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
reg = <0x22000 0x4>,
|
|
<0x22010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): ipu_pwrdm, ipu_clkdm */
|
|
clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x22000 0x1000>;
|
|
|
|
timer6: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@24000 { /* 0x48824000, ap 9 26.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
reg = <0x24000 0x4>,
|
|
<0x24010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): ipu_pwrdm, ipu_clkdm */
|
|
clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x24000 0x1000>;
|
|
|
|
timer7: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@26000 { /* 0x48826000, ap 11 0c.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
reg = <0x26000 0x4>,
|
|
<0x26010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): ipu_pwrdm, ipu_clkdm */
|
|
clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x26000 0x1000>;
|
|
|
|
timer8: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@28000 { /* 0x48828000, ap 13 16.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
reg = <0x28000 0x4>,
|
|
<0x28010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
|
|
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x28000 0x1000>;
|
|
|
|
timer13: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@2a000 { /* 0x4882a000, ap 15 10.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
reg = <0x2a000 0x4>,
|
|
<0x2a010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
|
|
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x2a000 0x1000>;
|
|
|
|
timer14: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
reg = <0x2c000 0x4>,
|
|
<0x2c010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
|
|
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x2c000 0x1000>;
|
|
|
|
timer15: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
reg = <0x2e000 0x4>,
|
|
<0x2e010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
|
|
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x2e000 0x1000>;
|
|
|
|
timer16: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */
|
|
compatible = "ti,sysc-omap4-simple", "ti,sysc";
|
|
ti,hwmods = "rtcss";
|
|
reg = <0x38074 0x4>,
|
|
<0x38078 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): rtc_pwrdm, rtc_clkdm */
|
|
clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x38000 0x1000>;
|
|
|
|
rtc: rtc@0 {
|
|
compatible = "ti,am3352-rtc";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&sys_32k_ck>;
|
|
};
|
|
};
|
|
|
|
target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x3a000 0x4>,
|
|
<0x3a010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x3a000 0x1000>;
|
|
|
|
mailbox2: mailbox@0 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
ti,mbox-num-users = <4>;
|
|
ti,mbox-num-fifos = <12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x3c000 0x4>,
|
|
<0x3c010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x3c000 0x1000>;
|
|
|
|
mailbox3: mailbox@0 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
ti,mbox-num-users = <4>;
|
|
ti,mbox-num-fifos = <12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@3e000 { /* 0x4883e000, ap 37 46.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x3e000 0x4>,
|
|
<0x3e010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x3e000 0x1000>;
|
|
|
|
mailbox4: mailbox@0 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
ti,mbox-num-users = <4>;
|
|
ti,mbox-num-fifos = <12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@40000 { /* 0x48840000, ap 39 64.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x40000 0x4>,
|
|
<0x40010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x40000 0x1000>;
|
|
|
|
mailbox5: mailbox@0 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
ti,mbox-num-users = <4>;
|
|
ti,mbox-num-fifos = <12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@42000 { /* 0x48842000, ap 41 4e.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x42000 0x4>,
|
|
<0x42010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x42000 0x1000>;
|
|
|
|
mailbox6: mailbox@0 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
ti,mbox-num-users = <4>;
|
|
ti,mbox-num-fifos = <12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@44000 { /* 0x48844000, ap 43 42.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x44000 0x4>,
|
|
<0x44010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x44000 0x1000>;
|
|
|
|
mailbox7: mailbox@0 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
ti,mbox-num-users = <4>;
|
|
ti,mbox-num-fifos = <12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@46000 { /* 0x48846000, ap 45 48.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x46000 0x4>,
|
|
<0x46010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x46000 0x1000>;
|
|
|
|
mailbox8: mailbox@0 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
ti,mbox-num-users = <4>;
|
|
ti,mbox-num-fifos = <12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@48000 { /* 0x48848000, ap 47 36.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x48000 0x1000>;
|
|
};
|
|
|
|
target-module@4a000 { /* 0x4884a000, ap 49 38.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x4a000 0x1000>;
|
|
};
|
|
|
|
target-module@4c000 { /* 0x4884c000, ap 51 44.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x4c000 0x1000>;
|
|
};
|
|
|
|
target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x4e000 0x1000>;
|
|
};
|
|
|
|
target-module@50000 { /* 0x48850000, ap 55 40.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x50000 0x1000>;
|
|
};
|
|
|
|
target-module@52000 { /* 0x48852000, ap 57 54.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x52000 0x1000>;
|
|
};
|
|
|
|
target-module@54000 { /* 0x48854000, ap 59 1a.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x54000 0x1000>;
|
|
};
|
|
|
|
target-module@56000 { /* 0x48856000, ap 61 22.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x56000 0x1000>;
|
|
};
|
|
|
|
target-module@58000 { /* 0x48858000, ap 63 2a.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x58000 0x1000>;
|
|
};
|
|
|
|
target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x5a000 0x1000>;
|
|
};
|
|
|
|
target-module@5c000 { /* 0x4885c000, ap 31 32.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x5c000 0x1000>;
|
|
};
|
|
|
|
target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x5e000 0x4>,
|
|
<0x5e010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x5e000 0x1000>;
|
|
|
|
mailbox9: mailbox@0 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
ti,mbox-num-users = <4>;
|
|
ti,mbox-num-fifos = <12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@60000 { /* 0x48860000, ap 71 4a.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x60000 0x4>,
|
|
<0x60010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x60000 0x1000>;
|
|
|
|
mailbox10: mailbox@0 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
ti,mbox-num-users = <4>;
|
|
ti,mbox-num-fifos = <12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@62000 { /* 0x48862000, ap 73 74.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x62000 0x4>,
|
|
<0x62010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x62000 0x1000>;
|
|
|
|
mailbox11: mailbox@0 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
ti,mbox-num-users = <4>;
|
|
ti,mbox-num-fifos = <12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@64000 { /* 0x48864000, ap 67 52.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x64000 0x4>,
|
|
<0x64010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
/* Domains (P, C): core_pwrdm, l4cfg_clkdm */
|
|
clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x64000 0x1000>;
|
|
|
|
mailbox12: mailbox@0 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <1>;
|
|
ti,mbox-num-users = <4>;
|
|
ti,mbox-num-fifos = <12>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@80000 { /* 0x48880000, ap 83 0e.1 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
ti,hwmods = "usb_otg_ss1";
|
|
reg = <0x80000 0x4>,
|
|
<0x80010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l3init_pwrdm, l3init_clkdm */
|
|
clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x80000 0x20000>;
|
|
|
|
omap_dwc3_1: omap_dwc3_1@0 {
|
|
compatible = "ti,dwc3";
|
|
reg = <0x0 0x10000>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
utmi-mode = <2>;
|
|
ranges = <0 0 0x20000>;
|
|
|
|
usb1: usb@10000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x10000 0x17000>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "peripheral",
|
|
"host",
|
|
"otg";
|
|
phys = <&usb2_phy1>, <&usb3_phy1>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
maximum-speed = "super-speed";
|
|
dr_mode = "otg";
|
|
snps,dis_u3_susphy_quirk;
|
|
snps,dis_u2_susphy_quirk;
|
|
};
|
|
};
|
|
};
|
|
|
|
target-module@c0000 { /* 0x488c0000, ap 79 06.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
ti,hwmods = "usb_otg_ss2";
|
|
reg = <0xc0000 0x4>,
|
|
<0xc0010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l3init_pwrdm, l3init_clkdm */
|
|
clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xc0000 0x20000>;
|
|
|
|
omap_dwc3_2: omap_dwc3_2@0 {
|
|
compatible = "ti,dwc3";
|
|
reg = <0x0 0x10000>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
utmi-mode = <2>;
|
|
ranges = <0 0 0x20000>;
|
|
|
|
usb2: usb@10000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x10000 0x17000>;
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "peripheral",
|
|
"host",
|
|
"otg";
|
|
phys = <&usb2_phy2>;
|
|
phy-names = "usb2-phy";
|
|
maximum-speed = "high-speed";
|
|
dr_mode = "otg";
|
|
snps,dis_u3_susphy_quirk;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_metastability_quirk;
|
|
};
|
|
};
|
|
};
|
|
|
|
usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
ti,hwmods = "usb_otg_ss3";
|
|
reg = <0x100000 0x4>,
|
|
<0x100010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l3init_pwrdm, l3init_clkdm */
|
|
clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x100000 0x20000>;
|
|
|
|
omap_dwc3_3: omap_dwc3_3@0 {
|
|
compatible = "ti,dwc3";
|
|
reg = <0x0 0x10000>;
|
|
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
utmi-mode = <2>;
|
|
ranges = <0 0 0x20000>;
|
|
status = "disabled";
|
|
|
|
usb3: usb@10000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x10000 0x17000>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "peripheral",
|
|
"host",
|
|
"otg";
|
|
maximum-speed = "high-speed";
|
|
dr_mode = "otg";
|
|
snps,dis_u3_susphy_quirk;
|
|
snps,dis_u2_susphy_quirk;
|
|
};
|
|
};
|
|
};
|
|
|
|
usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
ti,hwmods = "usb_otg_ss4";
|
|
reg = <0x140000 0x4>,
|
|
<0x140010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): l3init_pwrdm, l3init_clkdm */
|
|
clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x140000 0x20000>;
|
|
};
|
|
|
|
target-module@170000 { /* 0x48970000, ap 21 0a.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x170010 0x4>;
|
|
reg-names = "sysc";
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x170000 0x10000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
target-module@190000 { /* 0x48990000, ap 23 2e.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x190010 0x4>;
|
|
reg-names = "sysc";
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x190000 0x10000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x1b0000 0x4>,
|
|
<0x1b0010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x1b0000 0x10000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x1d0010 0x4>;
|
|
reg-names = "sysc";
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x1d0000 0x10000>;
|
|
|
|
vpe: vpe@0 {
|
|
compatible = "ti,dra7-vpe";
|
|
reg = <0x0000 0x120>,
|
|
<0x0700 0x80>,
|
|
<0x5700 0x18>,
|
|
<0xd000 0x400>;
|
|
reg-names = "vpe_top",
|
|
"sc",
|
|
"csc",
|
|
"vpdma";
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&l4_wkup { /* 0x4ae00000 */
|
|
compatible = "ti,dra7-l4-wkup", "simple-bus";
|
|
reg = <0x4ae00000 0x800>,
|
|
<0x4ae00800 0x800>,
|
|
<0x4ae01000 0x1000>;
|
|
reg-names = "ap", "la", "ia0";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
|
|
<0x00010000 0x4ae10000 0x010000>, /* segment 1 */
|
|
<0x00020000 0x4ae20000 0x010000>, /* segment 2 */
|
|
<0x00030000 0x4ae30000 0x010000>; /* segment 3 */
|
|
|
|
segment@0 { /* 0x4ae00000 */
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
|
|
<0x00001000 0x00001000 0x001000>, /* ap 1 */
|
|
<0x00000800 0x00000800 0x000800>, /* ap 2 */
|
|
<0x00006000 0x00006000 0x002000>, /* ap 3 */
|
|
<0x00008000 0x00008000 0x001000>, /* ap 4 */
|
|
<0x00004000 0x00004000 0x001000>, /* ap 15 */
|
|
<0x00005000 0x00005000 0x001000>, /* ap 16 */
|
|
<0x0000c000 0x0000c000 0x001000>, /* ap 17 */
|
|
<0x0000d000 0x0000d000 0x001000>; /* ap 18 */
|
|
|
|
target-module@4000 { /* 0x4ae04000, ap 15 40.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
ti,hwmods = "counter_32k";
|
|
reg = <0x4000 0x4>,
|
|
<0x4010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
|
|
clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x4000 0x1000>;
|
|
|
|
counter32k: counter@0 {
|
|
compatible = "ti,omap-counter32k";
|
|
reg = <0x0 0x40>;
|
|
};
|
|
};
|
|
|
|
target-module@6000 { /* 0x4ae06000, ap 3 10.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x6000 0x4>;
|
|
reg-names = "rev";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x6000 0x2000>;
|
|
|
|
prm: prm@0 {
|
|
compatible = "ti,dra7-prm", "simple-bus";
|
|
reg = <0 0x3000>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0x3000>;
|
|
|
|
prm_clocks: clocks {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
prm_clockdomains: clockdomains {
|
|
};
|
|
};
|
|
};
|
|
|
|
target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0xc000 0x4>;
|
|
reg-names = "rev";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xc000 0x1000>;
|
|
|
|
scm_wkup: scm_conf@0 {
|
|
compatible = "syscon";
|
|
reg = <0 0x1000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
segment@10000 { /* 0x4ae10000 */
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
|
|
<0x00001000 0x00011000 0x001000>, /* ap 6 */
|
|
<0x00004000 0x00014000 0x001000>, /* ap 7 */
|
|
<0x00005000 0x00015000 0x001000>, /* ap 8 */
|
|
<0x00008000 0x00018000 0x001000>, /* ap 9 */
|
|
<0x00009000 0x00019000 0x001000>, /* ap 10 */
|
|
<0x0000c000 0x0001c000 0x001000>, /* ap 11 */
|
|
<0x0000d000 0x0001d000 0x001000>; /* ap 12 */
|
|
|
|
target-module@0 { /* 0x4ae10000, ap 5 20.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x0 0x4>,
|
|
<0x10 0x4>,
|
|
<0x114 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
|
|
clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
|
|
<&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>;
|
|
clock-names = "fck", "dbclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0x1000>;
|
|
|
|
gpio1: gpio@0 {
|
|
compatible = "ti,omap4-gpio";
|
|
reg = <0x0 0x200>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
target-module@4000 { /* 0x4ae14000, ap 7 28.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x4000 0x4>,
|
|
<0x4010 0x4>,
|
|
<0x4014 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
|
|
SYSC_OMAP2_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
|
|
clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x4000 0x1000>;
|
|
|
|
wdt2: wdt@0 {
|
|
compatible = "ti,omap3-wdt";
|
|
reg = <0x0 0x80>;
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
ti,hwmods = "timer1";
|
|
reg = <0x8000 0x4>,
|
|
<0x8010 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
|
|
clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x8000 0x1000>;
|
|
|
|
timer1: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
|
|
clock-names = "fck";
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,timer-alwon;
|
|
};
|
|
};
|
|
|
|
target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xc000 0x1000>;
|
|
};
|
|
};
|
|
|
|
segment@20000 { /* 0x4ae20000 */
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
|
|
<0x0000a000 0x0002a000 0x001000>, /* ap 14 */
|
|
<0x00000000 0x00020000 0x001000>, /* ap 19 */
|
|
<0x00001000 0x00021000 0x001000>, /* ap 20 */
|
|
<0x00002000 0x00022000 0x001000>, /* ap 21 */
|
|
<0x00003000 0x00023000 0x001000>, /* ap 22 */
|
|
<0x00007000 0x00027000 0x000400>, /* ap 23 */
|
|
<0x00008000 0x00028000 0x000800>, /* ap 24 */
|
|
<0x00009000 0x00029000 0x000100>, /* ap 25 */
|
|
<0x00008800 0x00028800 0x000200>, /* ap 26 */
|
|
<0x00008a00 0x00028a00 0x000100>, /* ap 27 */
|
|
<0x0000b000 0x0002b000 0x001000>, /* ap 28 */
|
|
<0x0000c000 0x0002c000 0x001000>, /* ap 29 */
|
|
<0x0000f000 0x0002f000 0x001000>; /* ap 32 */
|
|
|
|
target-module@0 { /* 0x4ae20000, ap 19 08.0 */
|
|
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
|
reg = <0x0 0x4>,
|
|
<0x10 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
|
SYSC_OMAP4_SOFTRESET)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
/* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
|
|
clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0x1000>;
|
|
|
|
timer12: timer@0 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x0 0x80>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,timer-alwon;
|
|
ti,timer-secure;
|
|
};
|
|
};
|
|
|
|
target-module@2000 { /* 0x4ae22000, ap 21 18.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x2000 0x1000>;
|
|
};
|
|
|
|
target-module@6000 { /* 0x4ae26000, ap 13 48.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x00000000 0x00006000 0x00001000>,
|
|
<0x00001000 0x00007000 0x00000400>,
|
|
<0x00002000 0x00008000 0x00000800>,
|
|
<0x00002800 0x00008800 0x00000200>,
|
|
<0x00002a00 0x00008a00 0x00000100>,
|
|
<0x00003000 0x00009000 0x00000100>;
|
|
};
|
|
|
|
target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0xb050 0x4>,
|
|
<0xb054 0x4>,
|
|
<0xb058 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
|
|
clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xb000 0x1000>;
|
|
|
|
uart10: serial@0 {
|
|
compatible = "ti,dra742-uart", "ti,omap4-uart";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xf000 0x1000>;
|
|
};
|
|
};
|
|
|
|
segment@30000 { /* 0x4ae30000 */
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */
|
|
<0x0000e000 0x0003e000 0x001000>, /* ap 31 */
|
|
<0x00000000 0x00030000 0x001000>, /* ap 33 */
|
|
<0x00001000 0x00031000 0x001000>, /* ap 34 */
|
|
<0x00002000 0x00032000 0x001000>, /* ap 35 */
|
|
<0x00003000 0x00033000 0x001000>, /* ap 36 */
|
|
<0x00004000 0x00034000 0x001000>, /* ap 37 */
|
|
<0x00005000 0x00035000 0x001000>, /* ap 38 */
|
|
<0x00006000 0x00036000 0x001000>, /* ap 39 */
|
|
<0x00007000 0x00037000 0x001000>, /* ap 40 */
|
|
<0x00008000 0x00038000 0x001000>, /* ap 41 */
|
|
<0x00009000 0x00039000 0x001000>, /* ap 42 */
|
|
<0x0000a000 0x0003a000 0x001000>; /* ap 43 */
|
|
|
|
target-module@1000 { /* 0x4ae31000, ap 34 60.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x1000 0x1000>;
|
|
};
|
|
|
|
target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x3000 0x1000>;
|
|
};
|
|
|
|
target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x5000 0x1000>;
|
|
};
|
|
|
|
target-module@7000 { /* 0x4ae37000, ap 40 68.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x7000 0x1000>;
|
|
};
|
|
|
|
target-module@9000 { /* 0x4ae39000, ap 42 70.0 */
|
|
compatible = "ti,sysc";
|
|
status = "disabled";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x9000 0x1000>;
|
|
};
|
|
|
|
target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0xc020 0x4>;
|
|
reg-names = "rev";
|
|
clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xc000 0x2000>;
|
|
|
|
dcan1: can@0 {
|
|
compatible = "ti,dra7-d_can";
|
|
reg = <0x0 0x2000>;
|
|
syscon-raminit = <&scm_conf 0x558 0>;
|
|
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|