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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6a4a459580
Clearfog boards can come with a CPU clocked at 1600MHz (commercial) or 1333MHz (industrial). They have also some dip-switches to select a different clock (666, 800, 1066, 1200). The funny thing is that the recovery button is on the MPP34 fq selector. So, when booting an industrial board with this button down, the frequency 666MHz is selected (and the kernel didn't boot). This patch add all the missing clocks. The only mode I didn't test is 2GHz (uboot found 4294MHz instead :/ ). Fixes:0e85aeced4("clk: mvebu: add clock support for Armada 380/385") Cc: <stable@vger.kernel.org> # 3.16.x:9593f4f56c: clk: mvebu: armada-38x: add support for 1866MHz variants Cc: <stable@vger.kernel.org> # 3.16.x Signed-off-by: Richard Genoud <richard.genoud@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
169 lines
4.5 KiB
C
169 lines
4.5 KiB
C
/*
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* Marvell Armada 380/385 SoC clocks
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*
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* Copyright (C) 2014 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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* Andrew Lunn <andrew@lunn.ch>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include "common.h"
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/*
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* SAR[14:10] : Ratios between PCLK0, NBCLK, HCLK and DRAM clocks
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*
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* SAR[15] : TCLK frequency
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* 0 = 250 MHz
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* 1 = 200 MHz
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*/
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#define SAR_A380_TCLK_FREQ_OPT 15
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#define SAR_A380_TCLK_FREQ_OPT_MASK 0x1
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#define SAR_A380_CPU_DDR_L2_FREQ_OPT 10
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#define SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK 0x1F
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static const u32 armada_38x_tclk_frequencies[] __initconst = {
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250000000,
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200000000,
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};
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static u32 __init armada_38x_get_tclk_freq(void __iomem *sar)
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{
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u8 tclk_freq_select;
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tclk_freq_select = ((readl(sar) >> SAR_A380_TCLK_FREQ_OPT) &
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SAR_A380_TCLK_FREQ_OPT_MASK);
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return armada_38x_tclk_frequencies[tclk_freq_select];
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}
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static const u32 armada_38x_cpu_frequencies[] __initconst = {
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666 * 1000 * 1000, 0, 800 * 1000 * 1000, 0,
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1066 * 1000 * 1000, 0, 1200 * 1000 * 1000, 0,
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1332 * 1000 * 1000, 0, 0, 0,
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1600 * 1000 * 1000, 0, 0, 0,
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1866 * 1000 * 1000, 0, 0, 2000 * 1000 * 1000,
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};
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static u32 __init armada_38x_get_cpu_freq(void __iomem *sar)
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{
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u8 cpu_freq_select;
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cpu_freq_select = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) &
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SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK);
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if (cpu_freq_select >= ARRAY_SIZE(armada_38x_cpu_frequencies)) {
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pr_err("Selected CPU frequency (%d) unsupported\n",
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cpu_freq_select);
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return 0;
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}
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return armada_38x_cpu_frequencies[cpu_freq_select];
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}
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enum { A380_CPU_TO_DDR, A380_CPU_TO_L2 };
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static const struct coreclk_ratio armada_38x_coreclk_ratios[] __initconst = {
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{ .id = A380_CPU_TO_L2, .name = "l2clk" },
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{ .id = A380_CPU_TO_DDR, .name = "ddrclk" },
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};
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static const int armada_38x_cpu_l2_ratios[32][2] __initconst = {
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{1, 2}, {0, 1}, {1, 2}, {0, 1},
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{1, 2}, {0, 1}, {1, 2}, {0, 1},
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{1, 2}, {0, 1}, {0, 1}, {0, 1},
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{1, 2}, {0, 1}, {0, 1}, {0, 1},
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{1, 2}, {0, 1}, {0, 1}, {1, 2},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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};
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static const int armada_38x_cpu_ddr_ratios[32][2] __initconst = {
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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{1, 2}, {0, 1}, {0, 1}, {0, 1},
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{1, 2}, {0, 1}, {0, 1}, {0, 1},
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{1, 2}, {0, 1}, {0, 1}, {0, 1},
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{1, 2}, {0, 1}, {0, 1}, {7, 15},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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{0, 1}, {0, 1}, {0, 1}, {0, 1},
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};
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static void __init armada_38x_get_clk_ratio(
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void __iomem *sar, int id, int *mult, int *div)
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{
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u32 opt = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) &
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SAR_A380_CPU_DDR_L2_FREQ_OPT_MASK);
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switch (id) {
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case A380_CPU_TO_L2:
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*mult = armada_38x_cpu_l2_ratios[opt][0];
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*div = armada_38x_cpu_l2_ratios[opt][1];
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break;
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case A380_CPU_TO_DDR:
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*mult = armada_38x_cpu_ddr_ratios[opt][0];
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*div = armada_38x_cpu_ddr_ratios[opt][1];
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break;
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}
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}
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static const struct coreclk_soc_desc armada_38x_coreclks = {
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.get_tclk_freq = armada_38x_get_tclk_freq,
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.get_cpu_freq = armada_38x_get_cpu_freq,
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.get_clk_ratio = armada_38x_get_clk_ratio,
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.ratios = armada_38x_coreclk_ratios,
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.num_ratios = ARRAY_SIZE(armada_38x_coreclk_ratios),
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};
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static void __init armada_38x_coreclk_init(struct device_node *np)
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{
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mvebu_coreclk_setup(np, &armada_38x_coreclks);
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}
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CLK_OF_DECLARE(armada_38x_core_clk, "marvell,armada-380-core-clock",
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armada_38x_coreclk_init);
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/*
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* Clock Gating Control
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*/
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static const struct clk_gating_soc_desc armada_38x_gating_desc[] __initconst = {
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{ "audio", NULL, 0 },
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{ "ge2", NULL, 2 },
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{ "ge1", NULL, 3 },
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{ "ge0", NULL, 4 },
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{ "pex1", NULL, 5 },
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{ "pex2", NULL, 6 },
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{ "pex3", NULL, 7 },
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{ "pex0", NULL, 8 },
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{ "usb3h0", NULL, 9 },
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{ "usb3h1", NULL, 10 },
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{ "usb3d", NULL, 11 },
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{ "bm", NULL, 13 },
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{ "crypto0z", NULL, 14 },
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{ "sata0", NULL, 15 },
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{ "crypto1z", NULL, 16 },
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{ "sdio", NULL, 17 },
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{ "usb2", NULL, 18 },
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{ "crypto1", NULL, 21 },
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{ "xor0", NULL, 22 },
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{ "crypto0", NULL, 23 },
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{ "tdm", NULL, 25 },
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{ "xor1", NULL, 28 },
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{ "sata1", NULL, 30 },
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{ }
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};
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static void __init armada_38x_clk_gating_init(struct device_node *np)
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{
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mvebu_clk_gating_setup(np, armada_38x_gating_desc);
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}
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CLK_OF_DECLARE(armada_38x_clk_gating, "marvell,armada-380-gating-clock",
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armada_38x_clk_gating_init);
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