mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 19:06:46 +07:00
bba4ed011a
Provide support so that kexec can be used to boot a kernel when SME is enabled. Support is needed to allocate pages for kexec without encryption. This is needed in order to be able to reboot in the kernel in the same manner as originally booted. Additionally, when shutting down all of the CPUs we need to be sure to flush the caches and then halt. This is needed when booting from a state where SME was not active into a state where SME is active (or vice-versa). Without these steps, it is possible for cache lines to exist for the same physical location but tagged both with and without the encryption bit. This can cause random memory corruption when caches are flushed depending on which cacheline is written last. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Borislav Petkov <bp@suse.de> Cc: <kexec@lists.infradead.org> Cc: Alexander Potapenko <glider@google.com> Cc: Andrey Ryabinin <aryabinin@virtuozzo.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Brijesh Singh <brijesh.singh@amd.com> Cc: Dave Young <dyoung@redhat.com> Cc: Dmitry Vyukov <dvyukov@google.com> Cc: Jonathan Corbet <corbet@lwn.net> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Larry Woodman <lwoodman@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Matt Fleming <matt@codeblueprint.co.uk> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Rik van Riel <riel@redhat.com> Cc: Toshimitsu Kani <toshi.kani@hpe.com> Cc: kasan-dev@googlegroups.com Cc: kvm@vger.kernel.org Cc: linux-arch@vger.kernel.org Cc: linux-doc@vger.kernel.org Cc: linux-efi@vger.kernel.org Cc: linux-mm@kvack.org Link: http://lkml.kernel.org/r/b95ff075db3e7cd545313f2fb609a49619a09625.1500319216.git.thomas.lendacky@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
634 lines
15 KiB
C
634 lines
15 KiB
C
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/prctl.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/sched/idle.h>
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#include <linux/sched/debug.h>
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#include <linux/sched/task.h>
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#include <linux/sched/task_stack.h>
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/pm.h>
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#include <linux/tick.h>
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#include <linux/random.h>
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#include <linux/user-return-notifier.h>
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#include <linux/dmi.h>
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#include <linux/utsname.h>
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#include <linux/stackprotector.h>
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#include <linux/tick.h>
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#include <linux/cpuidle.h>
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#include <trace/events/power.h>
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#include <linux/hw_breakpoint.h>
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#include <asm/cpu.h>
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#include <asm/apic.h>
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#include <asm/syscalls.h>
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#include <linux/uaccess.h>
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#include <asm/mwait.h>
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#include <asm/fpu/internal.h>
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#include <asm/debugreg.h>
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#include <asm/nmi.h>
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#include <asm/tlbflush.h>
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#include <asm/mce.h>
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#include <asm/vm86.h>
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#include <asm/switch_to.h>
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#include <asm/desc.h>
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#include <asm/prctl.h>
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/*
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* per-CPU TSS segments. Threads are completely 'soft' on Linux,
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* no more per-task TSS's. The TSS size is kept cacheline-aligned
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* so they are allowed to end up in the .data..cacheline_aligned
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* section. Since TSS's are completely CPU-local, we want them
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* on exact cacheline boundaries, to eliminate cacheline ping-pong.
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*/
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__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = {
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.x86_tss = {
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.sp0 = TOP_OF_INIT_STACK,
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#ifdef CONFIG_X86_32
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.ss0 = __KERNEL_DS,
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.ss1 = __KERNEL_CS,
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.io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
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#endif
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},
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#ifdef CONFIG_X86_32
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/*
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* Note that the .io_bitmap member must be extra-big. This is because
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* the CPU will access an additional byte beyond the end of the IO
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* permission bitmap. The extra byte must be all 1 bits, and must
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* be within the limit.
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*/
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.io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
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#endif
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#ifdef CONFIG_X86_32
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.SYSENTER_stack_canary = STACK_END_MAGIC,
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#endif
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};
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EXPORT_PER_CPU_SYMBOL(cpu_tss);
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DEFINE_PER_CPU(bool, __tss_limit_invalid);
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EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
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/*
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* this gets called so that we can store lazy state into memory and copy the
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* current task into the new thread.
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*/
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int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
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{
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memcpy(dst, src, arch_task_struct_size);
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#ifdef CONFIG_VM86
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dst->thread.vm86 = NULL;
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#endif
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return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
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}
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/*
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* Free current thread data structures etc..
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*/
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void exit_thread(struct task_struct *tsk)
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{
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struct thread_struct *t = &tsk->thread;
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unsigned long *bp = t->io_bitmap_ptr;
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struct fpu *fpu = &t->fpu;
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if (bp) {
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struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu());
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t->io_bitmap_ptr = NULL;
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clear_thread_flag(TIF_IO_BITMAP);
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/*
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* Careful, clear this in the TSS too:
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*/
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memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
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t->io_bitmap_max = 0;
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put_cpu();
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kfree(bp);
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}
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free_vm86(t);
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fpu__drop(fpu);
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}
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void flush_thread(void)
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{
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struct task_struct *tsk = current;
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flush_ptrace_hw_breakpoint(tsk);
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memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
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fpu__clear(&tsk->thread.fpu);
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}
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void disable_TSC(void)
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{
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preempt_disable();
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if (!test_and_set_thread_flag(TIF_NOTSC))
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/*
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* Must flip the CPU state synchronously with
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* TIF_NOTSC in the current running context.
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*/
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cr4_set_bits(X86_CR4_TSD);
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preempt_enable();
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}
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static void enable_TSC(void)
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{
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preempt_disable();
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if (test_and_clear_thread_flag(TIF_NOTSC))
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/*
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* Must flip the CPU state synchronously with
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* TIF_NOTSC in the current running context.
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*/
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cr4_clear_bits(X86_CR4_TSD);
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preempt_enable();
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}
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int get_tsc_mode(unsigned long adr)
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{
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unsigned int val;
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if (test_thread_flag(TIF_NOTSC))
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val = PR_TSC_SIGSEGV;
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else
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val = PR_TSC_ENABLE;
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return put_user(val, (unsigned int __user *)adr);
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}
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int set_tsc_mode(unsigned int val)
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{
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if (val == PR_TSC_SIGSEGV)
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disable_TSC();
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else if (val == PR_TSC_ENABLE)
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enable_TSC();
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else
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return -EINVAL;
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return 0;
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}
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DEFINE_PER_CPU(u64, msr_misc_features_shadow);
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static void set_cpuid_faulting(bool on)
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{
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u64 msrval;
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msrval = this_cpu_read(msr_misc_features_shadow);
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msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
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msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
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this_cpu_write(msr_misc_features_shadow, msrval);
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wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
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}
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static void disable_cpuid(void)
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{
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preempt_disable();
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if (!test_and_set_thread_flag(TIF_NOCPUID)) {
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/*
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* Must flip the CPU state synchronously with
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* TIF_NOCPUID in the current running context.
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*/
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set_cpuid_faulting(true);
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}
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preempt_enable();
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}
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static void enable_cpuid(void)
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{
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preempt_disable();
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if (test_and_clear_thread_flag(TIF_NOCPUID)) {
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/*
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* Must flip the CPU state synchronously with
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* TIF_NOCPUID in the current running context.
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*/
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set_cpuid_faulting(false);
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}
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preempt_enable();
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}
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static int get_cpuid_mode(void)
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{
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return !test_thread_flag(TIF_NOCPUID);
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}
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static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
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{
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if (!static_cpu_has(X86_FEATURE_CPUID_FAULT))
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return -ENODEV;
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if (cpuid_enabled)
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enable_cpuid();
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else
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disable_cpuid();
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return 0;
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}
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/*
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* Called immediately after a successful exec.
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*/
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void arch_setup_new_exec(void)
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{
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/* If cpuid was previously disabled for this task, re-enable it. */
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if (test_thread_flag(TIF_NOCPUID))
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enable_cpuid();
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}
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static inline void switch_to_bitmap(struct tss_struct *tss,
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struct thread_struct *prev,
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struct thread_struct *next,
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unsigned long tifp, unsigned long tifn)
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{
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if (tifn & _TIF_IO_BITMAP) {
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/*
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* Copy the relevant range of the IO bitmap.
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* Normally this is 128 bytes or less:
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*/
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memcpy(tss->io_bitmap, next->io_bitmap_ptr,
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max(prev->io_bitmap_max, next->io_bitmap_max));
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/*
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* Make sure that the TSS limit is correct for the CPU
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* to notice the IO bitmap.
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*/
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refresh_tss_limit();
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} else if (tifp & _TIF_IO_BITMAP) {
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/*
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* Clear any possible leftover bits:
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*/
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memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
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}
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}
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void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
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struct tss_struct *tss)
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{
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struct thread_struct *prev, *next;
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unsigned long tifp, tifn;
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prev = &prev_p->thread;
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next = &next_p->thread;
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tifn = READ_ONCE(task_thread_info(next_p)->flags);
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tifp = READ_ONCE(task_thread_info(prev_p)->flags);
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switch_to_bitmap(tss, prev, next, tifp, tifn);
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propagate_user_return_notify(prev_p, next_p);
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if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
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arch_has_block_step()) {
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unsigned long debugctl, msk;
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rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
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debugctl &= ~DEBUGCTLMSR_BTF;
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msk = tifn & _TIF_BLOCKSTEP;
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debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
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wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
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}
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if ((tifp ^ tifn) & _TIF_NOTSC)
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cr4_toggle_bits(X86_CR4_TSD);
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if ((tifp ^ tifn) & _TIF_NOCPUID)
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set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
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}
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/*
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* Idle related variables and functions
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*/
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unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
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EXPORT_SYMBOL(boot_option_idle_override);
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static void (*x86_idle)(void);
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#ifndef CONFIG_SMP
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static inline void play_dead(void)
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{
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BUG();
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}
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#endif
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void arch_cpu_idle_enter(void)
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{
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tsc_verify_tsc_adjust(false);
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local_touch_nmi();
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}
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void arch_cpu_idle_dead(void)
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{
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play_dead();
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}
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/*
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* Called from the generic idle code.
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*/
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void arch_cpu_idle(void)
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{
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x86_idle();
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}
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/*
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* We use this if we don't have any better idle routine..
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*/
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void __cpuidle default_idle(void)
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{
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trace_cpu_idle_rcuidle(1, smp_processor_id());
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safe_halt();
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trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
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}
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#ifdef CONFIG_APM_MODULE
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EXPORT_SYMBOL(default_idle);
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#endif
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#ifdef CONFIG_XEN
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bool xen_set_default_idle(void)
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{
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bool ret = !!x86_idle;
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x86_idle = default_idle;
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return ret;
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}
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#endif
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void stop_this_cpu(void *dummy)
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{
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local_irq_disable();
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/*
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* Remove this CPU:
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*/
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set_cpu_online(smp_processor_id(), false);
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disable_local_APIC();
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mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
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for (;;) {
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/*
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* Use wbinvd followed by hlt to stop the processor. This
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* provides support for kexec on a processor that supports
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* SME. With kexec, going from SME inactive to SME active
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* requires clearing cache entries so that addresses without
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* the encryption bit set don't corrupt the same physical
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* address that has the encryption bit set when caches are
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* flushed. To achieve this a wbinvd is performed followed by
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* a hlt. Even if the processor is not in the kexec/SME
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* scenario this only adds a wbinvd to a halting processor.
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*/
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asm volatile("wbinvd; hlt" : : : "memory");
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}
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}
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/*
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* AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
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* states (local apic timer and TSC stop).
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*/
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static void amd_e400_idle(void)
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{
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/*
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* We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
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* gets set after static_cpu_has() places have been converted via
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* alternatives.
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*/
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if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
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default_idle();
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return;
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}
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tick_broadcast_enter();
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default_idle();
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/*
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* The switch back from broadcast mode needs to be called with
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* interrupts disabled.
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*/
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local_irq_disable();
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tick_broadcast_exit();
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local_irq_enable();
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}
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/*
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* Intel Core2 and older machines prefer MWAIT over HALT for C1.
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* We can't rely on cpuidle installing MWAIT, because it will not load
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* on systems that support only C1 -- so the boot default must be MWAIT.
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*
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* Some AMD machines are the opposite, they depend on using HALT.
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*
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* So for default C1, which is used during boot until cpuidle loads,
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* use MWAIT-C1 on Intel HW that has it, else use HALT.
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*/
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static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
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{
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if (c->x86_vendor != X86_VENDOR_INTEL)
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return 0;
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if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
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return 0;
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return 1;
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}
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/*
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* MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
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* with interrupts enabled and no flags, which is backwards compatible with the
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* original MWAIT implementation.
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*/
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static __cpuidle void mwait_idle(void)
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{
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if (!current_set_polling_and_test()) {
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trace_cpu_idle_rcuidle(1, smp_processor_id());
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if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
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mb(); /* quirk */
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clflush((void *)¤t_thread_info()->flags);
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mb(); /* quirk */
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}
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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if (!need_resched())
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__sti_mwait(0, 0);
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else
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local_irq_enable();
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trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
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} else {
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local_irq_enable();
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}
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__current_clr_polling();
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}
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void select_idle_routine(const struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_SMP
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if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
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pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
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#endif
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if (x86_idle || boot_option_idle_override == IDLE_POLL)
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return;
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if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
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pr_info("using AMD E400 aware idle routine\n");
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x86_idle = amd_e400_idle;
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} else if (prefer_mwait_c1_over_halt(c)) {
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pr_info("using mwait in idle threads\n");
|
|
x86_idle = mwait_idle;
|
|
} else
|
|
x86_idle = default_idle;
|
|
}
|
|
|
|
void amd_e400_c1e_apic_setup(void)
|
|
{
|
|
if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
|
|
pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
|
|
local_irq_disable();
|
|
tick_broadcast_force();
|
|
local_irq_enable();
|
|
}
|
|
}
|
|
|
|
void __init arch_post_acpi_subsys_init(void)
|
|
{
|
|
u32 lo, hi;
|
|
|
|
if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
|
|
return;
|
|
|
|
/*
|
|
* AMD E400 detection needs to happen after ACPI has been enabled. If
|
|
* the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
|
|
* MSR_K8_INT_PENDING_MSG.
|
|
*/
|
|
rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
|
|
if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
|
|
return;
|
|
|
|
boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
|
|
|
|
if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
|
|
mark_tsc_unstable("TSC halt in AMD C1E");
|
|
pr_info("System has AMD C1E enabled\n");
|
|
}
|
|
|
|
static int __init idle_setup(char *str)
|
|
{
|
|
if (!str)
|
|
return -EINVAL;
|
|
|
|
if (!strcmp(str, "poll")) {
|
|
pr_info("using polling idle threads\n");
|
|
boot_option_idle_override = IDLE_POLL;
|
|
cpu_idle_poll_ctrl(true);
|
|
} else if (!strcmp(str, "halt")) {
|
|
/*
|
|
* When the boot option of idle=halt is added, halt is
|
|
* forced to be used for CPU idle. In such case CPU C2/C3
|
|
* won't be used again.
|
|
* To continue to load the CPU idle driver, don't touch
|
|
* the boot_option_idle_override.
|
|
*/
|
|
x86_idle = default_idle;
|
|
boot_option_idle_override = IDLE_HALT;
|
|
} else if (!strcmp(str, "nomwait")) {
|
|
/*
|
|
* If the boot option of "idle=nomwait" is added,
|
|
* it means that mwait will be disabled for CPU C2/C3
|
|
* states. In such case it won't touch the variable
|
|
* of boot_option_idle_override.
|
|
*/
|
|
boot_option_idle_override = IDLE_NOMWAIT;
|
|
} else
|
|
return -1;
|
|
|
|
return 0;
|
|
}
|
|
early_param("idle", idle_setup);
|
|
|
|
unsigned long arch_align_stack(unsigned long sp)
|
|
{
|
|
if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
|
|
sp -= get_random_int() % 8192;
|
|
return sp & ~0xf;
|
|
}
|
|
|
|
unsigned long arch_randomize_brk(struct mm_struct *mm)
|
|
{
|
|
return randomize_page(mm->brk, 0x02000000);
|
|
}
|
|
|
|
/*
|
|
* Called from fs/proc with a reference on @p to find the function
|
|
* which called into schedule(). This needs to be done carefully
|
|
* because the task might wake up and we might look at a stack
|
|
* changing under us.
|
|
*/
|
|
unsigned long get_wchan(struct task_struct *p)
|
|
{
|
|
unsigned long start, bottom, top, sp, fp, ip, ret = 0;
|
|
int count = 0;
|
|
|
|
if (!p || p == current || p->state == TASK_RUNNING)
|
|
return 0;
|
|
|
|
if (!try_get_task_stack(p))
|
|
return 0;
|
|
|
|
start = (unsigned long)task_stack_page(p);
|
|
if (!start)
|
|
goto out;
|
|
|
|
/*
|
|
* Layout of the stack page:
|
|
*
|
|
* ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
|
|
* PADDING
|
|
* ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
|
|
* stack
|
|
* ----------- bottom = start
|
|
*
|
|
* The tasks stack pointer points at the location where the
|
|
* framepointer is stored. The data on the stack is:
|
|
* ... IP FP ... IP FP
|
|
*
|
|
* We need to read FP and IP, so we need to adjust the upper
|
|
* bound by another unsigned long.
|
|
*/
|
|
top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
|
|
top -= 2 * sizeof(unsigned long);
|
|
bottom = start;
|
|
|
|
sp = READ_ONCE(p->thread.sp);
|
|
if (sp < bottom || sp > top)
|
|
goto out;
|
|
|
|
fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
|
|
do {
|
|
if (fp < bottom || fp > top)
|
|
goto out;
|
|
ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
|
|
if (!in_sched_functions(ip)) {
|
|
ret = ip;
|
|
goto out;
|
|
}
|
|
fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
|
|
} while (count++ < 16 && p->state != TASK_RUNNING);
|
|
|
|
out:
|
|
put_task_stack(p);
|
|
return ret;
|
|
}
|
|
|
|
long do_arch_prctl_common(struct task_struct *task, int option,
|
|
unsigned long cpuid_enabled)
|
|
{
|
|
switch (option) {
|
|
case ARCH_GET_CPUID:
|
|
return get_cpuid_mode();
|
|
case ARCH_SET_CPUID:
|
|
return set_cpuid_mode(task, cpuid_enabled);
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|