mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 11:56:50 +07:00
bd7100099a
Convert some MIPS architecture's code to using struct syscore_ops objects for power management instead of sysdev classes and sysdevs. This simplifies the code and reduces the kernel's memory footprint. It also is necessary for removing sysdevs from the kernel entirely in the future. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Acked-and-tested-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-kernel@vger.kernel.org Cc: "Rafael J. Wysocki" <rjw@sisk.pl> Patchwork: http://patchwork.linux-mips.org/patch/2431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
586 lines
15 KiB
C
586 lines
15 KiB
C
/*
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* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 platform GPIO support
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/syscore_ops.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/bitops.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#include <asm/mach-jz4740/base.h>
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#define JZ4740_GPIO_BASE_A (32*0)
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#define JZ4740_GPIO_BASE_B (32*1)
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#define JZ4740_GPIO_BASE_C (32*2)
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#define JZ4740_GPIO_BASE_D (32*3)
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#define JZ4740_GPIO_NUM_A 32
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#define JZ4740_GPIO_NUM_B 32
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#define JZ4740_GPIO_NUM_C 31
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#define JZ4740_GPIO_NUM_D 32
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#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
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#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
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#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
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#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
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#define JZ_REG_GPIO_PIN 0x00
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#define JZ_REG_GPIO_DATA 0x10
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#define JZ_REG_GPIO_DATA_SET 0x14
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#define JZ_REG_GPIO_DATA_CLEAR 0x18
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#define JZ_REG_GPIO_MASK 0x20
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#define JZ_REG_GPIO_MASK_SET 0x24
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#define JZ_REG_GPIO_MASK_CLEAR 0x28
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#define JZ_REG_GPIO_PULL 0x30
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#define JZ_REG_GPIO_PULL_SET 0x34
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#define JZ_REG_GPIO_PULL_CLEAR 0x38
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#define JZ_REG_GPIO_FUNC 0x40
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#define JZ_REG_GPIO_FUNC_SET 0x44
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#define JZ_REG_GPIO_FUNC_CLEAR 0x48
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#define JZ_REG_GPIO_SELECT 0x50
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#define JZ_REG_GPIO_SELECT_SET 0x54
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#define JZ_REG_GPIO_SELECT_CLEAR 0x58
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#define JZ_REG_GPIO_DIRECTION 0x60
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#define JZ_REG_GPIO_DIRECTION_SET 0x64
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#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
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#define JZ_REG_GPIO_TRIGGER 0x70
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#define JZ_REG_GPIO_TRIGGER_SET 0x74
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#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
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#define JZ_REG_GPIO_FLAG 0x80
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#define JZ_REG_GPIO_FLAG_CLEAR 0x14
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#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
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#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
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#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
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struct jz_gpio_chip {
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unsigned int irq;
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unsigned int irq_base;
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uint32_t wakeup;
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uint32_t suspend_mask;
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uint32_t edge_trigger_both;
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void __iomem *base;
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spinlock_t lock;
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struct gpio_chip gpio_chip;
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};
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static struct jz_gpio_chip jz4740_gpio_chips[];
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static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
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{
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return &jz4740_gpio_chips[gpio >> 5];
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}
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static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip)
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{
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return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
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}
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static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data)
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{
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return irq_data_get_irq_chip_data(data);
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}
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static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
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{
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writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
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}
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int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
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{
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if (function == JZ_GPIO_FUNC_NONE) {
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jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
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jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
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jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
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} else {
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jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
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jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
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switch (function) {
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case JZ_GPIO_FUNC1:
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jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
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break;
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case JZ_GPIO_FUNC3:
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jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
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case JZ_GPIO_FUNC2: /* Falltrough */
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jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
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break;
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default:
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BUG();
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break;
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}
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(jz_gpio_set_function);
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int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
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{
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size_t i;
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int ret;
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for (i = 0; i < num; ++i, ++request) {
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ret = gpio_request(request->gpio, request->name);
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if (ret)
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goto err;
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jz_gpio_set_function(request->gpio, request->function);
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}
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return 0;
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err:
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for (--request; i > 0; --i, --request) {
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gpio_free(request->gpio);
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jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
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}
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return ret;
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}
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EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
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void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
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{
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size_t i;
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for (i = 0; i < num; ++i, ++request) {
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gpio_free(request->gpio);
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jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
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}
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}
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EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
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void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
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{
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size_t i;
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for (i = 0; i < num; ++i, ++request) {
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jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
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jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
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jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
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}
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}
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EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
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void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
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{
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size_t i;
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for (i = 0; i < num; ++i, ++request)
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jz_gpio_set_function(request->gpio, request->function);
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}
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EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
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void jz_gpio_enable_pullup(unsigned gpio)
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{
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jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
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}
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EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
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void jz_gpio_disable_pullup(unsigned gpio)
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{
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jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
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}
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EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
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static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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{
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return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
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}
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static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
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{
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uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
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reg += !value;
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writel(BIT(gpio), reg);
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}
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static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
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int value)
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{
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writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
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jz_gpio_set_value(chip, gpio, value);
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return 0;
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}
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static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
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return 0;
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}
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int jz_gpio_port_direction_input(int port, uint32_t mask)
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{
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writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
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return 0;
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}
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EXPORT_SYMBOL(jz_gpio_port_direction_input);
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int jz_gpio_port_direction_output(int port, uint32_t mask)
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{
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writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
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return 0;
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}
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EXPORT_SYMBOL(jz_gpio_port_direction_output);
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void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
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{
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writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
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writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
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}
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EXPORT_SYMBOL(jz_gpio_port_set_value);
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uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
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{
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uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
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return value & mask;
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}
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EXPORT_SYMBOL(jz_gpio_port_get_value);
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int gpio_to_irq(unsigned gpio)
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{
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return JZ4740_IRQ_GPIO(0) + gpio;
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}
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EXPORT_SYMBOL_GPL(gpio_to_irq);
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int irq_to_gpio(unsigned irq)
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{
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return irq - JZ4740_IRQ_GPIO(0);
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}
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EXPORT_SYMBOL_GPL(irq_to_gpio);
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#define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)
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static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq)
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{
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uint32_t value;
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void __iomem *reg;
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uint32_t mask = IRQ_TO_BIT(irq);
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if (!(chip->edge_trigger_both & mask))
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return;
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reg = chip->base;
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value = readl(chip->base + JZ_REG_GPIO_PIN);
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if (value & mask)
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reg += JZ_REG_GPIO_DIRECTION_CLEAR;
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else
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reg += JZ_REG_GPIO_DIRECTION_SET;
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writel(mask, reg);
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}
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static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
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{
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uint32_t flag;
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unsigned int gpio_irq;
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unsigned int gpio_bank;
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struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
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gpio_bank = JZ4740_IRQ_GPIO0 - irq;
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flag = readl(chip->base + JZ_REG_GPIO_FLAG);
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if (!flag)
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return;
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gpio_irq = __fls(flag);
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jz_gpio_check_trigger_both(chip, irq);
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gpio_irq += (gpio_bank << 5) + JZ4740_IRQ_GPIO(0);
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generic_handle_irq(gpio_irq);
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};
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static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg)
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{
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struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
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writel(IRQ_TO_BIT(data->irq), chip->base + reg);
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}
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static void jz_gpio_irq_mask(struct irq_data *data)
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{
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_SET);
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};
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static void jz_gpio_irq_unmask(struct irq_data *data)
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{
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struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
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jz_gpio_check_trigger_both(chip, data->irq);
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_MASK_CLEAR);
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};
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/* TODO: Check if function is gpio */
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static unsigned int jz_gpio_irq_startup(struct irq_data *data)
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{
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET);
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jz_gpio_irq_unmask(data);
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return 0;
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}
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static void jz_gpio_irq_shutdown(struct irq_data *data)
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{
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jz_gpio_irq_mask(data);
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/* Set direction to input */
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR);
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}
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static void jz_gpio_irq_ack(struct irq_data *data)
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{
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_FLAG_CLEAR);
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};
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static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
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{
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struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
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unsigned int irq = data->irq;
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if (flow_type == IRQ_TYPE_EDGE_BOTH) {
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uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
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if (value & IRQ_TO_BIT(irq))
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flow_type = IRQ_TYPE_EDGE_FALLING;
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else
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flow_type = IRQ_TYPE_EDGE_RISING;
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chip->edge_trigger_both |= IRQ_TO_BIT(irq);
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} else {
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chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
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}
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switch (flow_type) {
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case IRQ_TYPE_EDGE_RISING:
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET);
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR);
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jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
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{
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struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data);
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spin_lock(&chip->lock);
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if (on)
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chip->wakeup |= IRQ_TO_BIT(data->irq);
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else
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chip->wakeup &= ~IRQ_TO_BIT(data->irq);
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spin_unlock(&chip->lock);
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irq_set_irq_wake(chip->irq, on);
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return 0;
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}
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static struct irq_chip jz_gpio_irq_chip = {
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.name = "GPIO",
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.irq_mask = jz_gpio_irq_mask,
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.irq_unmask = jz_gpio_irq_unmask,
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.irq_ack = jz_gpio_irq_ack,
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.irq_startup = jz_gpio_irq_startup,
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.irq_shutdown = jz_gpio_irq_shutdown,
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.irq_set_type = jz_gpio_irq_set_type,
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.irq_set_wake = jz_gpio_irq_set_wake,
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.flags = IRQCHIP_SET_TYPE_MASKED,
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};
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/*
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* This lock class tells lockdep that GPIO irqs are in a different
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* category than their parents, so it won't report false recursion.
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*/
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static struct lock_class_key gpio_lock_class;
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#define JZ4740_GPIO_CHIP(_bank) { \
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.irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
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.gpio_chip = { \
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.label = "Bank " # _bank, \
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.owner = THIS_MODULE, \
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.set = jz_gpio_set_value, \
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.get = jz_gpio_get_value, \
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.direction_output = jz_gpio_direction_output, \
|
|
.direction_input = jz_gpio_direction_input, \
|
|
.base = JZ4740_GPIO_BASE_ ## _bank, \
|
|
.ngpio = JZ4740_GPIO_NUM_ ## _bank, \
|
|
}, \
|
|
}
|
|
|
|
static struct jz_gpio_chip jz4740_gpio_chips[] = {
|
|
JZ4740_GPIO_CHIP(A),
|
|
JZ4740_GPIO_CHIP(B),
|
|
JZ4740_GPIO_CHIP(C),
|
|
JZ4740_GPIO_CHIP(D),
|
|
};
|
|
|
|
static void jz4740_gpio_suspend_chip(struct jz_gpio_chip *chip)
|
|
{
|
|
chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
|
|
writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
|
|
writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
|
|
}
|
|
|
|
static int jz4740_gpio_suspend(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); i++)
|
|
jz4740_gpio_suspend_chip(&jz4740_gpio_chips[i]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void jz4740_gpio_resume_chip(struct jz_gpio_chip *chip)
|
|
{
|
|
uint32_t mask = chip->suspend_mask;
|
|
|
|
writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
|
|
writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
|
|
}
|
|
|
|
static void jz4740_gpio_resume(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = ARRAY_SIZE(jz4740_gpio_chips) - 1; i >= 0 ; i--)
|
|
jz4740_gpio_resume_chip(&jz4740_gpio_chips[i]);
|
|
}
|
|
|
|
static struct syscore_ops jz4740_gpio_syscore_ops = {
|
|
.suspend = jz4740_gpio_suspend,
|
|
.resume = jz4740_gpio_resume,
|
|
};
|
|
|
|
static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
|
|
{
|
|
int irq;
|
|
|
|
spin_lock_init(&chip->lock);
|
|
|
|
chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100);
|
|
|
|
gpiochip_add(&chip->gpio_chip);
|
|
|
|
chip->irq = JZ4740_IRQ_INTC_GPIO(id);
|
|
irq_set_handler_data(chip->irq, chip);
|
|
irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
|
|
|
|
for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
|
|
irq_set_lockdep_class(irq, &gpio_lock_class);
|
|
irq_set_chip_data(irq, chip);
|
|
irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
|
|
handle_level_irq);
|
|
}
|
|
}
|
|
|
|
static int __init jz4740_gpio_init(void)
|
|
{
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i)
|
|
jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
|
|
|
|
register_syscore_ops(&jz4740_gpio_syscore_ops);
|
|
|
|
printk(KERN_INFO "JZ4740 GPIO initialized\n");
|
|
|
|
return 0;
|
|
}
|
|
arch_initcall(jz4740_gpio_init);
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
|
|
const char *name, unsigned int reg)
|
|
{
|
|
seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
|
|
}
|
|
|
|
static int gpio_regs_show(struct seq_file *s, void *unused)
|
|
{
|
|
struct jz_gpio_chip *chip = jz4740_gpio_chips;
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
|
|
seq_printf(s, "==GPIO %d==\n", i);
|
|
gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
|
|
gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
|
|
gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
|
|
gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
|
|
gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
|
|
gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
|
|
gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
|
|
gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
|
|
gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int gpio_regs_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, gpio_regs_show, NULL);
|
|
}
|
|
|
|
static const struct file_operations gpio_regs_operations = {
|
|
.open = gpio_regs_open,
|
|
.read = seq_read,
|
|
.llseek = seq_lseek,
|
|
.release = single_release,
|
|
};
|
|
|
|
static int __init gpio_debugfs_init(void)
|
|
{
|
|
(void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
|
|
NULL, NULL, &gpio_regs_operations);
|
|
return 0;
|
|
}
|
|
subsys_initcall(gpio_debugfs_init);
|
|
|
|
#endif
|