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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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be604c616c
Clang's integrated assembler does not allow assembly macros defined in one inline asm block using the .macro directive to be used across separate asm blocks. LLVM developers consider this a feature and not a bug, recommending code refactoring: https://bugs.llvm.org/show_bug.cgi?id=19749 As binutils doesn't allow macros to be redefined, this change uses UNDEFINE_MRS_S and UNDEFINE_MSR_S to define corresponding macros in-place and workaround gcc and clang limitations on redefining macros across different assembler blocks. Specifically, the current state after preprocessing looks like this: asm volatile(".macro mXX_s ... .endm"); void f() { asm volatile("mXX_s a, b"); } With GCC, it gives macro redefinition error because sysreg.h is included in multiple source files, and assembler code for all of them is later combined for LTO (I've seen an intermediate file with hundreds of identical definitions). With clang, it gives macro undefined error because clang doesn't allow sharing macros between inline asm statements. I also seem to remember catching another sort of undefined error with GCC due to reordering of macro definition asm statement and generated asm code for function that uses the macro. The solution with defining and undefining for each use, while certainly not elegant, satisfies both GCC and clang, LTO and non-LTO. Co-developed-by: Alex Matveev <alxmtvv@gmail.com> Co-developed-by: Yury Norov <ynorov@caviumnetworks.com> Co-developed-by: Sami Tolvanen <samitolvanen@google.com> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Kees Cook <keescook@chromium.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
145 lines
3.3 KiB
C
145 lines
3.3 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_IRQFLAGS_H
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#define __ASM_IRQFLAGS_H
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#ifdef __KERNEL__
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#include <asm/alternative.h>
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#include <asm/ptrace.h>
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#include <asm/sysreg.h>
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/*
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* Aarch64 has flags for masking: Debug, Asynchronous (serror), Interrupts and
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* FIQ exceptions, in the 'daif' register. We mask and unmask them in 'dai'
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* order:
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* Masking debug exceptions causes all other exceptions to be masked too/
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* Masking SError masks irq, but not debug exceptions. Masking irqs has no
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* side effects for other flags. Keeping to this order makes it easier for
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* entry.S to know which exceptions should be unmasked.
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*
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* FIQ is never expected, but we mask it when we disable debug exceptions, and
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* unmask it at all other times.
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*/
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/*
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* CPU interrupt mask handling.
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*/
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static inline void arch_local_irq_enable(void)
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{
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asm volatile(ALTERNATIVE(
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"msr daifclr, #2 // arch_local_irq_enable\n"
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"nop",
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__msr_s(SYS_ICC_PMR_EL1, "%0")
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"dsb sy",
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ARM64_HAS_IRQ_PRIO_MASKING)
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:
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: "r" ((unsigned long) GIC_PRIO_IRQON)
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: "memory");
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}
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static inline void arch_local_irq_disable(void)
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{
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asm volatile(ALTERNATIVE(
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"msr daifset, #2 // arch_local_irq_disable",
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__msr_s(SYS_ICC_PMR_EL1, "%0"),
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ARM64_HAS_IRQ_PRIO_MASKING)
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:
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: "r" ((unsigned long) GIC_PRIO_IRQOFF)
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: "memory");
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}
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/*
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* Save the current interrupt enable state.
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*/
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static inline unsigned long arch_local_save_flags(void)
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{
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unsigned long daif_bits;
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unsigned long flags;
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daif_bits = read_sysreg(daif);
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/*
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* The asm is logically equivalent to:
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*
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* if (system_uses_irq_prio_masking())
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* flags = (daif_bits & PSR_I_BIT) ?
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* GIC_PRIO_IRQOFF :
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* read_sysreg_s(SYS_ICC_PMR_EL1);
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* else
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* flags = daif_bits;
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*/
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asm volatile(ALTERNATIVE(
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"mov %0, %1\n"
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"nop\n"
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"nop",
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__mrs_s("%0", SYS_ICC_PMR_EL1)
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"ands %1, %1, " __stringify(PSR_I_BIT) "\n"
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"csel %0, %0, %2, eq",
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ARM64_HAS_IRQ_PRIO_MASKING)
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: "=&r" (flags), "+r" (daif_bits)
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: "r" ((unsigned long) GIC_PRIO_IRQOFF)
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: "memory");
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return flags;
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}
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static inline unsigned long arch_local_irq_save(void)
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{
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unsigned long flags;
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flags = arch_local_save_flags();
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arch_local_irq_disable();
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return flags;
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}
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/*
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* restore saved IRQ state
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*/
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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asm volatile(ALTERNATIVE(
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"msr daif, %0\n"
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"nop",
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__msr_s(SYS_ICC_PMR_EL1, "%0")
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"dsb sy",
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ARM64_HAS_IRQ_PRIO_MASKING)
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: "+r" (flags)
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:
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: "memory");
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}
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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int res;
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asm volatile(ALTERNATIVE(
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"and %w0, %w1, #" __stringify(PSR_I_BIT) "\n"
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"nop",
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"cmp %w1, #" __stringify(GIC_PRIO_IRQOFF) "\n"
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"cset %w0, ls",
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ARM64_HAS_IRQ_PRIO_MASKING)
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: "=&r" (res)
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: "r" ((int) flags)
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: "memory");
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return res;
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}
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#endif
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#endif
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