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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6f74dc9bc8
Enhance the driver to dynamically allocate the base IRQ number, and create an IRQ domain for itself. The use of an IRQ domain ensures that any device tree node interrupts properties are correctly parsed. Describe interrupt-related properties in the device tree binding docs, and the contents of "child" node interrupts property. Update tegra*.dtsi to specify the required interrupt-related properties. Finally, remove the definition of TEGRA_GPIO_TO_IRQ; this macro no longer gives correct results since the IRQ numbers for GPIOs are dynamically allocated. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Olof Johansson <olof@lixom.net>
179 lines
4.0 KiB
Plaintext
179 lines
4.0 KiB
Plaintext
/include/ "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra30";
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interrupt-parent = <&intc>;
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pmc@7000f400 {
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compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
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reg = <0x7000e400 0x400>;
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};
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intc: interrupt-controller@50041000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = < 0x50041000 0x1000 >,
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< 0x50040100 0x0100 >;
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};
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apbdma: dma@6000a000 {
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compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
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reg = <0x6000a000 0x1400>;
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interrupts = < 0 104 0x04
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0 105 0x04
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0 106 0x04
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0 107 0x04
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0 108 0x04
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0 109 0x04
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0 110 0x04
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0 111 0x04
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0 112 0x04
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0 113 0x04
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0 114 0x04
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0 115 0x04
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0 116 0x04
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0 117 0x04
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0 118 0x04
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0 119 0x04
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0 128 0x04
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0 129 0x04
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0 130 0x04
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0 131 0x04
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0 132 0x04
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0 133 0x04
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0 134 0x04
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0 135 0x04
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0 136 0x04
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0 137 0x04
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0 138 0x04
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0 139 0x04
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0 140 0x04
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0 141 0x04
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0 142 0x04
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0 143 0x04 >;
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};
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i2c@7000c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000C000 0x100>;
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interrupts = < 0 38 0x04 >;
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};
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i2c@7000c400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000C400 0x100>;
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interrupts = < 0 84 0x04 >;
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};
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i2c@7000c500 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000C500 0x100>;
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interrupts = < 0 92 0x04 >;
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};
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i2c@7000c700 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000c700 0x100>;
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interrupts = < 0 120 0x04 >;
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};
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i2c@7000d000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
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reg = <0x7000D000 0x100>;
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interrupts = < 0 53 0x04 >;
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};
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
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reg = < 0x6000d000 0x1000 >;
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interrupts = < 0 32 0x04
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0 33 0x04
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0 34 0x04
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0 35 0x04
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0 55 0x04
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0 87 0x04
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0 89 0x04
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0 125 0x04 >;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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serial@70006000 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = < 0 36 0x04 >;
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};
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serial@70006040 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = < 0 37 0x04 >;
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};
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serial@70006200 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = < 0 46 0x04 >;
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};
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serial@70006300 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = < 0 90 0x04 >;
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};
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serial@70006400 {
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compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
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reg = <0x70006400 0x100>;
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reg-shift = <2>;
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interrupts = < 0 91 0x04 >;
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};
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sdhci@78000000 {
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compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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reg = <0x78000000 0x200>;
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interrupts = < 0 14 0x04 >;
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};
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sdhci@78000200 {
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compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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reg = <0x78000200 0x200>;
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interrupts = < 0 15 0x04 >;
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};
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sdhci@78000400 {
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compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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reg = <0x78000400 0x200>;
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interrupts = < 0 19 0x04 >;
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};
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sdhci@78000600 {
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compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
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reg = <0x78000600 0x200>;
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interrupts = < 0 31 0x04 >;
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};
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pinmux: pinmux@70000000 {
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compatible = "nvidia,tegra30-pinmux";
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reg = < 0x70000868 0xd0 /* Pad control registers */
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0x70003000 0x3e0 >; /* Mux registers */
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};
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};
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