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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Based on 1 normalized pattern(s): this software is licensed under the terms of the gnu general public license version 2 as published by the free software foundation and may be copied distributed and modified under those terms this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 285 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.642774971@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
242 lines
6.0 KiB
C
242 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2010 Marvell International Ltd.
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* Zhangfei Gao <zhangfei.gao@marvell.com>
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* Kevin Wang <dwang4@marvell.com>
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* Jun Nie <njun@marvell.com>
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* Qiming Wu <wuqm@marvell.com>
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* Philip Rakity <prakity@marvell.com>
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/host.h>
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#include <linux/platform_data/pxa_sdhci.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include "sdhci.h"
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#include "sdhci-pltfm.h"
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#define SD_FIFO_PARAM 0xe0
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#define DIS_PAD_SD_CLK_GATE 0x0400 /* Turn on/off Dynamic SD Clock Gating */
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#define CLK_GATE_ON 0x0200 /* Disable/enable Clock Gate */
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#define CLK_GATE_CTL 0x0100 /* Clock Gate Control */
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#define CLK_GATE_SETTING_BITS (DIS_PAD_SD_CLK_GATE | \
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CLK_GATE_ON | CLK_GATE_CTL)
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#define SD_CLOCK_BURST_SIZE_SETUP 0xe6
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#define SDCLK_SEL_SHIFT 8
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#define SDCLK_SEL_MASK 0x3
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#define SDCLK_DELAY_SHIFT 10
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#define SDCLK_DELAY_MASK 0x3c
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#define SD_CE_ATA_2 0xea
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#define MMC_CARD 0x1000
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#define MMC_WIDTH 0x0100
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static void pxav2_reset(struct sdhci_host *host, u8 mask)
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{
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struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
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struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
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sdhci_reset(host, mask);
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if (mask == SDHCI_RESET_ALL) {
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u16 tmp = 0;
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/*
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* tune timing of read data/command when crc error happen
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* no performance impact
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*/
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if (pdata && pdata->clk_delay_sel == 1) {
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tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
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tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
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tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
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<< SDCLK_DELAY_SHIFT;
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tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
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tmp |= (1 & SDCLK_SEL_MASK) << SDCLK_SEL_SHIFT;
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writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
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}
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if (pdata && (pdata->flags & PXA_FLAG_ENABLE_CLOCK_GATING)) {
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tmp = readw(host->ioaddr + SD_FIFO_PARAM);
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tmp &= ~CLK_GATE_SETTING_BITS;
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writew(tmp, host->ioaddr + SD_FIFO_PARAM);
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} else {
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tmp = readw(host->ioaddr + SD_FIFO_PARAM);
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tmp &= ~CLK_GATE_SETTING_BITS;
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tmp |= CLK_GATE_SETTING_BITS;
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writew(tmp, host->ioaddr + SD_FIFO_PARAM);
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}
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}
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}
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static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width)
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{
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u8 ctrl;
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u16 tmp;
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ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
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tmp = readw(host->ioaddr + SD_CE_ATA_2);
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if (width == MMC_BUS_WIDTH_8) {
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ctrl &= ~SDHCI_CTRL_4BITBUS;
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tmp |= MMC_CARD | MMC_WIDTH;
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} else {
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tmp &= ~(MMC_CARD | MMC_WIDTH);
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if (width == MMC_BUS_WIDTH_4)
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ctrl |= SDHCI_CTRL_4BITBUS;
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else
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ctrl &= ~SDHCI_CTRL_4BITBUS;
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}
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writew(tmp, host->ioaddr + SD_CE_ATA_2);
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writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
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}
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static const struct sdhci_ops pxav2_sdhci_ops = {
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.set_clock = sdhci_set_clock,
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.get_max_clock = sdhci_pltfm_clk_get_max_clock,
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.set_bus_width = pxav2_mmc_set_bus_width,
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.reset = pxav2_reset,
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.set_uhs_signaling = sdhci_set_uhs_signaling,
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};
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#ifdef CONFIG_OF
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static const struct of_device_id sdhci_pxav2_of_match[] = {
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{
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.compatible = "mrvl,pxav2-mmc",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match);
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static struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
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{
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struct sdhci_pxa_platdata *pdata;
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struct device_node *np = dev->of_node;
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u32 bus_width;
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u32 clk_delay_cycles;
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pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
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if (!pdata)
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return NULL;
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if (of_find_property(np, "non-removable", NULL))
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pdata->flags |= PXA_FLAG_CARD_PERMANENT;
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of_property_read_u32(np, "bus-width", &bus_width);
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if (bus_width == 8)
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pdata->flags |= PXA_FLAG_SD_8_BIT_CAPABLE_SLOT;
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of_property_read_u32(np, "mrvl,clk-delay-cycles", &clk_delay_cycles);
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if (clk_delay_cycles > 0) {
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pdata->clk_delay_sel = 1;
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pdata->clk_delay_cycles = clk_delay_cycles;
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}
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return pdata;
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}
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#else
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static inline struct sdhci_pxa_platdata *pxav2_get_mmc_pdata(struct device *dev)
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{
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return NULL;
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}
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#endif
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static int sdhci_pxav2_probe(struct platform_device *pdev)
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{
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
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struct device *dev = &pdev->dev;
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struct sdhci_host *host = NULL;
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const struct of_device_id *match;
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int ret;
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struct clk *clk;
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host = sdhci_pltfm_init(pdev, NULL, 0);
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if (IS_ERR(host))
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return PTR_ERR(host);
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pltfm_host = sdhci_priv(host);
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clk = devm_clk_get(dev, "PXA-SDHCLK");
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if (IS_ERR(clk)) {
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dev_err(dev, "failed to get io clock\n");
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ret = PTR_ERR(clk);
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goto free;
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}
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pltfm_host->clk = clk;
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ret = clk_prepare_enable(clk);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable io clock\n");
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goto free;
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}
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host->quirks = SDHCI_QUIRK_BROKEN_ADMA
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| SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
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| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
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match = of_match_device(of_match_ptr(sdhci_pxav2_of_match), &pdev->dev);
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if (match) {
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pdata = pxav2_get_mmc_pdata(dev);
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}
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if (pdata) {
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if (pdata->flags & PXA_FLAG_CARD_PERMANENT) {
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/* on-chip device */
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host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
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host->mmc->caps |= MMC_CAP_NONREMOVABLE;
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}
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/* If slot design supports 8 bit data, indicate this to MMC. */
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if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
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host->mmc->caps |= MMC_CAP_8_BIT_DATA;
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if (pdata->quirks)
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host->quirks |= pdata->quirks;
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if (pdata->host_caps)
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host->mmc->caps |= pdata->host_caps;
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if (pdata->pm_caps)
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host->mmc->pm_caps |= pdata->pm_caps;
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}
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host->ops = &pxav2_sdhci_ops;
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ret = sdhci_add_host(host);
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if (ret)
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goto disable_clk;
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return 0;
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disable_clk:
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clk_disable_unprepare(clk);
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free:
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sdhci_pltfm_free(pdev);
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return ret;
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}
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static struct platform_driver sdhci_pxav2_driver = {
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.driver = {
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.name = "sdhci-pxav2",
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.of_match_table = of_match_ptr(sdhci_pxav2_of_match),
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.pm = &sdhci_pltfm_pmops,
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},
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.probe = sdhci_pxav2_probe,
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.remove = sdhci_pltfm_unregister,
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};
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module_platform_driver(sdhci_pxav2_driver);
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MODULE_DESCRIPTION("SDHCI driver for pxav2");
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MODULE_AUTHOR("Marvell International Ltd.");
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MODULE_LICENSE("GPL v2");
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