mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 13:28:57 +07:00
a0e37da2a5
The omap_gpio_dev_attr data was used to supply instance-specific
data for legacy non-DT devices. The GPIO legacy device support has
been cleaned up in commit 14944934f8 ("ARM: OMAP2+: Remove legacy
gpio code") a while ago and this data is therefore no longer needed.
So, cleanup the structure and all the associated data in various
hwmod data files.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
220 lines
6.4 KiB
C
220 lines
6.4 KiB
C
/*
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* OMAP GPIO handling defines and functions
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*
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* Copyright (C) 2003-2005 Nokia Corporation
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*
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* Written by Juha Yrjölä <juha.yrjola@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __ASM_ARCH_OMAP_GPIO_H
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#define __ASM_ARCH_OMAP_GPIO_H
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#define OMAP1_MPUIO_BASE 0xfffb5000
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/*
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* These are the omap15xx/16xx offsets. The omap7xx offset are
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* OMAP_MPUIO_ / 2 offsets below.
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*/
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#define OMAP_MPUIO_INPUT_LATCH 0x00
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#define OMAP_MPUIO_OUTPUT 0x04
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#define OMAP_MPUIO_IO_CNTL 0x08
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#define OMAP_MPUIO_KBR_LATCH 0x10
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#define OMAP_MPUIO_KBC 0x14
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#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
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#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
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#define OMAP_MPUIO_KBD_INT 0x20
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#define OMAP_MPUIO_GPIO_INT 0x24
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#define OMAP_MPUIO_KBD_MASKIT 0x28
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#define OMAP_MPUIO_GPIO_MASKIT 0x2c
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#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
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#define OMAP_MPUIO_LATCH 0x34
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#define OMAP34XX_NR_GPIOS 6
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/*
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* OMAP1510 GPIO registers
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*/
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#define OMAP1510_GPIO_DATA_INPUT 0x00
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#define OMAP1510_GPIO_DATA_OUTPUT 0x04
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#define OMAP1510_GPIO_DIR_CONTROL 0x08
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#define OMAP1510_GPIO_INT_CONTROL 0x0c
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#define OMAP1510_GPIO_INT_MASK 0x10
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#define OMAP1510_GPIO_INT_STATUS 0x14
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#define OMAP1510_GPIO_PIN_CONTROL 0x18
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#define OMAP1510_IH_GPIO_BASE 64
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/*
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* OMAP1610 specific GPIO registers
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*/
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#define OMAP1610_GPIO_REVISION 0x0000
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#define OMAP1610_GPIO_SYSCONFIG 0x0010
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#define OMAP1610_GPIO_SYSSTATUS 0x0014
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#define OMAP1610_GPIO_IRQSTATUS1 0x0018
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#define OMAP1610_GPIO_IRQENABLE1 0x001c
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#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
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#define OMAP1610_GPIO_DATAIN 0x002c
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#define OMAP1610_GPIO_DATAOUT 0x0030
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#define OMAP1610_GPIO_DIRECTION 0x0034
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#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
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#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
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#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
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#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
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#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
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#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
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#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
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#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
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/*
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* OMAP7XX specific GPIO registers
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*/
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#define OMAP7XX_GPIO_DATA_INPUT 0x00
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#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
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#define OMAP7XX_GPIO_DIR_CONTROL 0x08
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#define OMAP7XX_GPIO_INT_CONTROL 0x0c
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#define OMAP7XX_GPIO_INT_MASK 0x10
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#define OMAP7XX_GPIO_INT_STATUS 0x14
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/*
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* omap2+ specific GPIO registers
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*/
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#define OMAP24XX_GPIO_REVISION 0x0000
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#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
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#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
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#define OMAP24XX_GPIO_IRQENABLE2 0x002c
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#define OMAP24XX_GPIO_IRQENABLE1 0x001c
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#define OMAP24XX_GPIO_WAKE_EN 0x0020
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#define OMAP24XX_GPIO_CTRL 0x0030
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#define OMAP24XX_GPIO_OE 0x0034
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#define OMAP24XX_GPIO_DATAIN 0x0038
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#define OMAP24XX_GPIO_DATAOUT 0x003c
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#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
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#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
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#define OMAP24XX_GPIO_RISINGDETECT 0x0048
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#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
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#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
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#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
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#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
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#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
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#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
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#define OMAP24XX_GPIO_SETWKUENA 0x0084
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#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
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#define OMAP24XX_GPIO_SETDATAOUT 0x0094
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#define OMAP4_GPIO_REVISION 0x0000
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#define OMAP4_GPIO_EOI 0x0020
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#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
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#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
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#define OMAP4_GPIO_IRQSTATUS0 0x002c
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#define OMAP4_GPIO_IRQSTATUS1 0x0030
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#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
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#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
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#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
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#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
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#define OMAP4_GPIO_IRQWAKEN0 0x0044
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#define OMAP4_GPIO_IRQWAKEN1 0x0048
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#define OMAP4_GPIO_IRQENABLE1 0x011c
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#define OMAP4_GPIO_WAKE_EN 0x0120
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#define OMAP4_GPIO_IRQSTATUS2 0x0128
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#define OMAP4_GPIO_IRQENABLE2 0x012c
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#define OMAP4_GPIO_CTRL 0x0130
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#define OMAP4_GPIO_OE 0x0134
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#define OMAP4_GPIO_DATAIN 0x0138
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#define OMAP4_GPIO_DATAOUT 0x013c
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#define OMAP4_GPIO_LEVELDETECT0 0x0140
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#define OMAP4_GPIO_LEVELDETECT1 0x0144
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#define OMAP4_GPIO_RISINGDETECT 0x0148
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#define OMAP4_GPIO_FALLINGDETECT 0x014c
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#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
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#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
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#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
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#define OMAP4_GPIO_SETIRQENABLE1 0x0164
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#define OMAP4_GPIO_CLEARWKUENA 0x0180
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#define OMAP4_GPIO_SETWKUENA 0x0184
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#define OMAP4_GPIO_CLEARDATAOUT 0x0190
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#define OMAP4_GPIO_SETDATAOUT 0x0194
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#define OMAP_MAX_GPIO_LINES 192
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#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
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#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
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struct omap_gpio_reg_offs {
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u16 revision;
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u16 direction;
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u16 datain;
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u16 dataout;
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u16 set_dataout;
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u16 clr_dataout;
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u16 irqstatus;
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u16 irqstatus2;
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u16 irqstatus_raw0;
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u16 irqstatus_raw1;
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u16 irqenable;
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u16 irqenable2;
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u16 set_irqenable;
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u16 clr_irqenable;
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u16 debounce;
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u16 debounce_en;
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u16 ctrl;
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u16 wkup_en;
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u16 leveldetect0;
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u16 leveldetect1;
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u16 risingdetect;
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u16 fallingdetect;
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u16 irqctrl;
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u16 edgectrl1;
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u16 edgectrl2;
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u16 pinctrl;
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bool irqenable_inv;
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};
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struct omap_gpio_platform_data {
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int bank_type;
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int bank_width; /* GPIO bank width */
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int bank_stride; /* Only needed for omap1 MPUIO */
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bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
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bool loses_context; /* whether the bank would ever lose context */
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bool is_mpuio; /* whether the bank is of type MPUIO */
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u32 non_wakeup_gpios;
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struct omap_gpio_reg_offs *regs;
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/* Return context loss count due to PM states changing */
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int (*get_context_loss_count)(struct device *dev);
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};
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#if IS_BUILTIN(CONFIG_GPIO_OMAP)
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extern void omap2_gpio_prepare_for_idle(int off_mode);
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extern void omap2_gpio_resume_after_idle(void);
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#else
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static inline void omap2_gpio_prepare_for_idle(int off_mode)
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{
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}
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static inline void omap2_gpio_resume_after_idle(void)
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{
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}
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#endif
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#endif
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