mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 00:36:42 +07:00
23759dc643
Patch from Lennert Buytenhek This patch adds support for the I/O coherent cache available on the xsc3. The approach is to provide a simple API to determine whether the chipset supports coherency by calling arch_is_coherent() and then setting the appropriate system memory PTE and PMD bits. In addition, we call this API on dma_alloc_coherent() and dma_map_single() calls. A generic version exists that will compile out all the coherency-related code that is not needed on the majority of ARM systems. Note that we do not check for coherency in the dma_alloc_writecombine() function as that still requires a special PTE setting. We also don't touch dma_mmap_coherent() as that is a special ARM-only API that is by definition only used on non-coherent system. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
90 lines
2.5 KiB
C
90 lines
2.5 KiB
C
/*
|
|
* linux/include/asm-arm/pgtable-hwdef.h
|
|
*
|
|
* Copyright (C) 1995-2002 Russell King
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
#ifndef _ASMARM_PGTABLE_HWDEF_H
|
|
#define _ASMARM_PGTABLE_HWDEF_H
|
|
|
|
/*
|
|
* Hardware page table definitions.
|
|
*
|
|
* + Level 1 descriptor (PMD)
|
|
* - common
|
|
*/
|
|
#define PMD_TYPE_MASK (3 << 0)
|
|
#define PMD_TYPE_FAULT (0 << 0)
|
|
#define PMD_TYPE_TABLE (1 << 0)
|
|
#define PMD_TYPE_SECT (2 << 0)
|
|
#define PMD_BIT4 (1 << 4)
|
|
#define PMD_DOMAIN(x) ((x) << 5)
|
|
#define PMD_PROTECTION (1 << 9) /* v5 */
|
|
/*
|
|
* - section
|
|
*/
|
|
#define PMD_SECT_BUFFERABLE (1 << 2)
|
|
#define PMD_SECT_CACHEABLE (1 << 3)
|
|
#define PMD_SECT_AP_WRITE (1 << 10)
|
|
#define PMD_SECT_AP_READ (1 << 11)
|
|
#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
|
|
#define PMD_SECT_APX (1 << 15) /* v6 */
|
|
#define PMD_SECT_S (1 << 16) /* v6 */
|
|
#define PMD_SECT_nG (1 << 17) /* v6 */
|
|
#define PMD_SECT_SUPER (1 << 18) /* v6 */
|
|
|
|
#define PMD_SECT_UNCACHED (0)
|
|
#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
|
|
#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
|
|
#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
|
|
#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
|
|
#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
|
|
#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
|
|
|
|
/*
|
|
* - coarse table (not used)
|
|
*/
|
|
|
|
/*
|
|
* + Level 2 descriptor (PTE)
|
|
* - common
|
|
*/
|
|
#define PTE_TYPE_MASK (3 << 0)
|
|
#define PTE_TYPE_FAULT (0 << 0)
|
|
#define PTE_TYPE_LARGE (1 << 0)
|
|
#define PTE_TYPE_SMALL (2 << 0)
|
|
#define PTE_TYPE_EXT (3 << 0) /* v5 */
|
|
#define PTE_BUFFERABLE (1 << 2)
|
|
#define PTE_CACHEABLE (1 << 3)
|
|
|
|
/*
|
|
* - extended small page/tiny page
|
|
*/
|
|
#define PTE_EXT_XN (1 << 0) /* v6 */
|
|
#define PTE_EXT_AP_MASK (3 << 4)
|
|
#define PTE_EXT_AP0 (1 << 4)
|
|
#define PTE_EXT_AP1 (2 << 4)
|
|
#define PTE_EXT_AP_UNO_SRO (0 << 4)
|
|
#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
|
|
#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
|
|
#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
|
|
#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
|
|
#define PTE_EXT_APX (1 << 9) /* v6 */
|
|
#define PTE_EXT_COHERENT (1 << 9) /* XScale3 */
|
|
#define PTE_EXT_SHARED (1 << 10) /* v6 */
|
|
#define PTE_EXT_NG (1 << 11) /* v6 */
|
|
|
|
/*
|
|
* - small page
|
|
*/
|
|
#define PTE_SMALL_AP_MASK (0xff << 4)
|
|
#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
|
|
#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
|
|
#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
|
|
#define PTE_SMALL_AP_URW_SRW (0xff << 4)
|
|
|
|
#endif
|