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76b235c6bc
Since we've already stepped away from ENABLE is a JMP and DISABLE is a
NOP with the branch_default bits, and are going to make it even worse,
rename it to make it all clearer.
This way we don't mix multiple levels of logic attributes, but have a
plain 'physical' name for what the current instruction patching status
of a jump label is.
This is a first step in removing the naming confusion that has led to
a stream of avoidable bugs such as:
a833581e37 ("x86, perf: Fix static_key bug in load_mm_cr4()")
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
[ Beefed up the changelog. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
77 lines
2.1 KiB
C
77 lines
2.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 2010 Cavium Networks, Inc.
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*/
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#include <linux/jump_label.h>
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#include <linux/kernel.h>
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#include <linux/memory.h>
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#include <linux/mutex.h>
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#include <linux/types.h>
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#include <linux/cpu.h>
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#include <asm/cacheflush.h>
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#include <asm/inst.h>
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#ifdef HAVE_JUMP_LABEL
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/*
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* Define parameters for the standard MIPS and the microMIPS jump
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* instruction encoding respectively:
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*
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* - the ISA bit of the target, either 0 or 1 respectively,
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*
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* - the amount the jump target address is shifted right to fit in the
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* immediate field of the machine instruction, either 2 or 1,
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*
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* - the mask determining the size of the jump region relative to the
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* delay-slot instruction, either 256MB or 128MB,
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*
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* - the jump target alignment, either 4 or 2 bytes.
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*/
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#define J_ISA_BIT IS_ENABLED(CONFIG_CPU_MICROMIPS)
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#define J_RANGE_SHIFT (2 - J_ISA_BIT)
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#define J_RANGE_MASK ((1ul << (26 + J_RANGE_SHIFT)) - 1)
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#define J_ALIGN_MASK ((1ul << J_RANGE_SHIFT) - 1)
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void arch_jump_label_transform(struct jump_entry *e,
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enum jump_label_type type)
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{
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union mips_instruction *insn_p;
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union mips_instruction insn;
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insn_p = (union mips_instruction *)msk_isa16_mode(e->code);
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/* Jump only works within an aligned region its delay slot is in. */
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BUG_ON((e->target & ~J_RANGE_MASK) != ((e->code + 4) & ~J_RANGE_MASK));
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/* Target must have the right alignment and ISA must be preserved. */
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BUG_ON((e->target & J_ALIGN_MASK) != J_ISA_BIT);
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if (type == JUMP_LABEL_JMP) {
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insn.j_format.opcode = J_ISA_BIT ? mm_j32_op : j_op;
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insn.j_format.target = e->target >> J_RANGE_SHIFT;
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} else {
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insn.word = 0; /* nop */
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}
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get_online_cpus();
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mutex_lock(&text_mutex);
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if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) {
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insn_p->halfword[0] = insn.word >> 16;
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insn_p->halfword[1] = insn.word;
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} else
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*insn_p = insn;
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flush_icache_range((unsigned long)insn_p,
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(unsigned long)insn_p + sizeof(*insn_p));
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mutex_unlock(&text_mutex);
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put_online_cpus();
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}
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#endif /* HAVE_JUMP_LABEL */
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