mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6ea0297e39
NVIDIA's Tegra114 has 6 SPI controllers. These controllers are redesign on T114 with different register interface. Add DT entry for spi controllers and make it compatible with "nvidia,tegra114-spi", since they are a new incompatible design. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: fixed reg property for 3rd SPI controller] Signed-off-by: Stephen Warren <swarren@nvidia.com>
394 lines
8.6 KiB
Plaintext
394 lines
8.6 KiB
Plaintext
/include/ "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra114";
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uarta;
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serial1 = &uartb;
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serial2 = &uartc;
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serial3 = &uartd;
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};
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gic: interrupt-controller {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x50041000 0x1000>,
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<0x50042000 0x1000>,
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<0x50044000 0x2000>,
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<0x50046000 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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timer@60005000 {
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compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
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reg = <0x60005000 0x400>;
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interrupts = <0 0 0x04
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0 1 0x04
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0 41 0x04
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0 42 0x04
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0 121 0x04
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0 122 0x04>;
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clocks = <&tegra_car 5>;
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};
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tegra_car: clock {
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compatible = "nvidia,tegra114-car";
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reg = <0x60006000 0x1000>;
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#clock-cells = <1>;
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};
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apbdma: dma {
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compatible = "nvidia,tegra114-apbdma";
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reg = <0x6000a000 0x1400>;
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interrupts = <0 104 0x04
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0 105 0x04
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0 106 0x04
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0 107 0x04
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0 108 0x04
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0 109 0x04
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0 110 0x04
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0 111 0x04
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0 112 0x04
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0 113 0x04
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0 114 0x04
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0 115 0x04
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0 116 0x04
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0 117 0x04
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0 118 0x04
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0 119 0x04
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0 128 0x04
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0 129 0x04
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0 130 0x04
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0 131 0x04
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0 132 0x04
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0 133 0x04
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0 134 0x04
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0 135 0x04
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0 136 0x04
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0 137 0x04
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0 138 0x04
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0 139 0x04
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0 140 0x04
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0 141 0x04
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0 142 0x04
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0 143 0x04>;
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clocks = <&tegra_car 34>;
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};
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ahb: ahb {
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compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
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reg = <0x6000c004 0x14c>;
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};
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gpio: gpio {
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compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
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reg = <0x6000d000 0x1000>;
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interrupts = <0 32 0x04
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0 33 0x04
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0 34 0x04
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0 35 0x04
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0 55 0x04
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0 87 0x04
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0 89 0x04
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0 125 0x04>;
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#gpio-cells = <2>;
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gpio-controller;
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#interrupt-cells = <2>;
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interrupt-controller;
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};
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pinmux: pinmux {
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compatible = "nvidia,tegra114-pinmux";
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reg = <0x70000868 0x148 /* Pad control registers */
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0x70003000 0x40c>; /* Mux registers */
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};
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/*
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* There are two serial driver i.e. 8250 based simple serial
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* driver and APB DMA based serial driver for higher baudrate
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* and performace. To enable the 8250 based driver, the compatible
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* is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
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* the APB DMA based serial driver, the comptible is
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* "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
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*/
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uarta: serial@70006000 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <0 36 0x04>;
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nvidia,dma-request-selector = <&apbdma 8>;
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status = "disabled";
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clocks = <&tegra_car 6>;
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};
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uartb: serial@70006040 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = <0 37 0x04>;
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nvidia,dma-request-selector = <&apbdma 9>;
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status = "disabled";
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clocks = <&tegra_car 192>;
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};
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uartc: serial@70006200 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = <0 46 0x04>;
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nvidia,dma-request-selector = <&apbdma 10>;
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status = "disabled";
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clocks = <&tegra_car 55>;
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};
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uartd: serial@70006300 {
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compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = <0 90 0x04>;
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nvidia,dma-request-selector = <&apbdma 19>;
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status = "disabled";
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clocks = <&tegra_car 65>;
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};
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pwm: pwm {
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compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
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reg = <0x7000a000 0x100>;
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#pwm-cells = <2>;
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clocks = <&tegra_car 17>;
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status = "disabled";
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};
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i2c@7000c000 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000c000 0x100>;
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interrupts = <0 38 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 12>;
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clock-names = "div-clk";
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status = "disabled";
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};
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i2c@7000c400 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000c400 0x100>;
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interrupts = <0 84 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 54>;
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clock-names = "div-clk";
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status = "disabled";
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};
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i2c@7000c500 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000c500 0x100>;
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interrupts = <0 92 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 67>;
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clock-names = "div-clk";
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status = "disabled";
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};
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i2c@7000c700 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000c700 0x100>;
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interrupts = <0 120 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 103>;
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clock-names = "div-clk";
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status = "disabled";
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};
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i2c@7000d000 {
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compatible = "nvidia,tegra114-i2c";
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reg = <0x7000d000 0x100>;
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interrupts = <0 53 0x04>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 47>;
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clock-names = "div-clk";
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status = "disabled";
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};
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spi@7000d400 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000d400 0x200>;
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interrupts = <0 59 0x04>;
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nvidia,dma-request-selector = <&apbdma 15>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 41>;
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clock-names = "spi";
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status = "disabled";
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};
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spi@7000d600 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000d600 0x200>;
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interrupts = <0 82 0x04>;
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nvidia,dma-request-selector = <&apbdma 16>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 44>;
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clock-names = "spi";
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status = "disabled";
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};
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spi@7000d800 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000d800 0x200>;
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interrupts = <0 83 0x04>;
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nvidia,dma-request-selector = <&apbdma 17>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 46>;
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clock-names = "spi";
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status = "disabled";
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};
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spi@7000da00 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000da00 0x200>;
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interrupts = <0 93 0x04>;
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nvidia,dma-request-selector = <&apbdma 18>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 68>;
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clock-names = "spi";
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status = "disabled";
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};
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spi@7000dc00 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000dc00 0x200>;
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interrupts = <0 94 0x04>;
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nvidia,dma-request-selector = <&apbdma 27>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 104>;
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clock-names = "spi";
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status = "disabled";
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};
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spi@7000de00 {
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compatible = "nvidia,tegra114-spi";
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reg = <0x7000de00 0x200>;
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interrupts = <0 79 0x04>;
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nvidia,dma-request-selector = <&apbdma 28>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&tegra_car 105>;
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clock-names = "spi";
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status = "disabled";
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};
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rtc {
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compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
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reg = <0x7000e000 0x100>;
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interrupts = <0 2 0x04>;
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clocks = <&tegra_car 4>;
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};
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kbc {
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compatible = "nvidia,tegra114-kbc";
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reg = <0x7000e200 0x100>;
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interrupts = <0 85 0x04>;
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clocks = <&tegra_car 36>;
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status = "disabled";
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};
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pmc {
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compatible = "nvidia,tegra114-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car 261>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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};
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iommu {
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compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
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reg = <0x7000f010 0x02c
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0x7000f1f0 0x010
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0x7000f228 0x074>;
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nvidia,#asids = <4>;
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dma-window = <0 0x40000000>;
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nvidia,swgroups = <0x18659fe>;
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nvidia,ahb = <&ahb>;
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};
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sdhci@78000000 {
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compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
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reg = <0x78000000 0x200>;
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interrupts = <0 14 0x04>;
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clocks = <&tegra_car 14>;
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status = "disable";
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};
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sdhci@78000200 {
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compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
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reg = <0x78000200 0x200>;
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interrupts = <0 15 0x04>;
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clocks = <&tegra_car 9>;
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status = "disable";
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};
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sdhci@78000400 {
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compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
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reg = <0x78000400 0x200>;
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interrupts = <0 19 0x04>;
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clocks = <&tegra_car 69>;
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status = "disable";
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};
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sdhci@78000600 {
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compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
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reg = <0x78000600 0x200>;
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interrupts = <0 31 0x04>;
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clocks = <&tegra_car 15>;
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status = "disable";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <3>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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};
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