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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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0b79b27748
The post_send() path determines if it should post directly or, schedule the post for later. The current logic is: if the swqe ring is empty or (for hfi1) wqe->length <= piothreshold post the send else schedule This can allow large requests to call the send engine directly. Large requests can potentially produce a large number of packets prior to returning to the caller, blocking the caller from posting more requests, and allowing better parallel processing. Allow the driver(s) more say in this logic (pass call_send to the driver, rather than examining a return value). Update hfi1/qib logic to schedule the send engine if an RC or UC message is larger than the QP MTU size. Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com> Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
455 lines
11 KiB
C
455 lines
11 KiB
C
/*
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* Copyright (c) 2012 - 2017 Intel Corporation. All rights reserved.
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* Copyright (c) 2006 - 2012 QLogic Corporation. * All rights reserved.
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* Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/err.h>
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#include <linux/vmalloc.h>
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#include <rdma/rdma_vt.h>
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#ifdef CONFIG_DEBUG_FS
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#include <linux/seq_file.h>
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#endif
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#include "qib.h"
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static inline unsigned mk_qpn(struct rvt_qpn_table *qpt,
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struct rvt_qpn_map *map, unsigned off)
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{
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return (map - qpt->map) * RVT_BITS_PER_PAGE + off;
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}
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static inline unsigned find_next_offset(struct rvt_qpn_table *qpt,
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struct rvt_qpn_map *map, unsigned off,
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unsigned n, u16 qpt_mask)
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{
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if (qpt_mask) {
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off++;
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if (((off & qpt_mask) >> 1) >= n)
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off = (off | qpt_mask) + 2;
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} else {
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off = find_next_zero_bit(map->page, RVT_BITS_PER_PAGE, off);
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}
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return off;
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}
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const struct rvt_operation_params qib_post_parms[RVT_OPERATION_MAX] = {
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[IB_WR_RDMA_WRITE] = {
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.length = sizeof(struct ib_rdma_wr),
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.qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
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},
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[IB_WR_RDMA_READ] = {
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.length = sizeof(struct ib_rdma_wr),
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.qpt_support = BIT(IB_QPT_RC),
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.flags = RVT_OPERATION_ATOMIC,
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},
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[IB_WR_ATOMIC_CMP_AND_SWP] = {
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.length = sizeof(struct ib_atomic_wr),
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.qpt_support = BIT(IB_QPT_RC),
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.flags = RVT_OPERATION_ATOMIC | RVT_OPERATION_ATOMIC_SGE,
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},
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[IB_WR_ATOMIC_FETCH_AND_ADD] = {
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.length = sizeof(struct ib_atomic_wr),
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.qpt_support = BIT(IB_QPT_RC),
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.flags = RVT_OPERATION_ATOMIC | RVT_OPERATION_ATOMIC_SGE,
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},
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[IB_WR_RDMA_WRITE_WITH_IMM] = {
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.length = sizeof(struct ib_rdma_wr),
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.qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
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},
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[IB_WR_SEND] = {
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.length = sizeof(struct ib_send_wr),
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.qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) |
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BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
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},
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[IB_WR_SEND_WITH_IMM] = {
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.length = sizeof(struct ib_send_wr),
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.qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) |
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BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
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},
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};
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static void get_map_page(struct rvt_qpn_table *qpt, struct rvt_qpn_map *map)
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{
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unsigned long page = get_zeroed_page(GFP_KERNEL);
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/*
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* Free the page if someone raced with us installing it.
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*/
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spin_lock(&qpt->lock);
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if (map->page)
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free_page(page);
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else
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map->page = (void *)page;
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spin_unlock(&qpt->lock);
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}
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/*
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* Allocate the next available QPN or
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* zero/one for QP type IB_QPT_SMI/IB_QPT_GSI.
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*/
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int qib_alloc_qpn(struct rvt_dev_info *rdi, struct rvt_qpn_table *qpt,
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enum ib_qp_type type, u8 port)
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{
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u32 i, offset, max_scan, qpn;
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struct rvt_qpn_map *map;
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u32 ret;
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struct qib_ibdev *verbs_dev = container_of(rdi, struct qib_ibdev, rdi);
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struct qib_devdata *dd = container_of(verbs_dev, struct qib_devdata,
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verbs_dev);
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u16 qpt_mask = dd->qpn_mask;
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if (type == IB_QPT_SMI || type == IB_QPT_GSI) {
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unsigned n;
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ret = type == IB_QPT_GSI;
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n = 1 << (ret + 2 * (port - 1));
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spin_lock(&qpt->lock);
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if (qpt->flags & n)
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ret = -EINVAL;
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else
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qpt->flags |= n;
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spin_unlock(&qpt->lock);
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goto bail;
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}
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qpn = qpt->last + 2;
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if (qpn >= RVT_QPN_MAX)
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qpn = 2;
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if (qpt_mask && ((qpn & qpt_mask) >> 1) >= dd->n_krcv_queues)
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qpn = (qpn | qpt_mask) + 2;
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offset = qpn & RVT_BITS_PER_PAGE_MASK;
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map = &qpt->map[qpn / RVT_BITS_PER_PAGE];
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max_scan = qpt->nmaps - !offset;
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for (i = 0;;) {
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if (unlikely(!map->page)) {
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get_map_page(qpt, map);
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if (unlikely(!map->page))
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break;
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}
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do {
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if (!test_and_set_bit(offset, map->page)) {
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qpt->last = qpn;
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ret = qpn;
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goto bail;
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}
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offset = find_next_offset(qpt, map, offset,
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dd->n_krcv_queues, qpt_mask);
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qpn = mk_qpn(qpt, map, offset);
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/*
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* This test differs from alloc_pidmap().
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* If find_next_offset() does find a zero
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* bit, we don't need to check for QPN
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* wrapping around past our starting QPN.
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* We just need to be sure we don't loop
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* forever.
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*/
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} while (offset < RVT_BITS_PER_PAGE && qpn < RVT_QPN_MAX);
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/*
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* In order to keep the number of pages allocated to a
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* minimum, we scan the all existing pages before increasing
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* the size of the bitmap table.
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*/
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if (++i > max_scan) {
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if (qpt->nmaps == RVT_QPNMAP_ENTRIES)
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break;
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map = &qpt->map[qpt->nmaps++];
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offset = 0;
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} else if (map < &qpt->map[qpt->nmaps]) {
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++map;
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offset = 0;
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} else {
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map = &qpt->map[0];
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offset = 2;
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}
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qpn = mk_qpn(qpt, map, offset);
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}
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ret = -ENOMEM;
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bail:
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return ret;
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}
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/**
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* qib_free_all_qps - check for QPs still in use
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*/
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unsigned qib_free_all_qps(struct rvt_dev_info *rdi)
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{
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struct qib_ibdev *verbs_dev = container_of(rdi, struct qib_ibdev, rdi);
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struct qib_devdata *dd = container_of(verbs_dev, struct qib_devdata,
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verbs_dev);
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unsigned n, qp_inuse = 0;
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for (n = 0; n < dd->num_pports; n++) {
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struct qib_ibport *ibp = &dd->pport[n].ibport_data;
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rcu_read_lock();
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if (rcu_dereference(ibp->rvp.qp[0]))
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qp_inuse++;
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if (rcu_dereference(ibp->rvp.qp[1]))
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qp_inuse++;
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rcu_read_unlock();
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}
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return qp_inuse;
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}
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void qib_notify_qp_reset(struct rvt_qp *qp)
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{
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struct qib_qp_priv *priv = qp->priv;
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atomic_set(&priv->s_dma_busy, 0);
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}
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void qib_notify_error_qp(struct rvt_qp *qp)
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{
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struct qib_qp_priv *priv = qp->priv;
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struct qib_ibdev *dev = to_idev(qp->ibqp.device);
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spin_lock(&dev->rdi.pending_lock);
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if (!list_empty(&priv->iowait) && !(qp->s_flags & RVT_S_BUSY)) {
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qp->s_flags &= ~RVT_S_ANY_WAIT_IO;
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list_del_init(&priv->iowait);
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}
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spin_unlock(&dev->rdi.pending_lock);
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if (!(qp->s_flags & RVT_S_BUSY)) {
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qp->s_hdrwords = 0;
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if (qp->s_rdma_mr) {
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rvt_put_mr(qp->s_rdma_mr);
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qp->s_rdma_mr = NULL;
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}
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if (priv->s_tx) {
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qib_put_txreq(priv->s_tx);
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priv->s_tx = NULL;
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}
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}
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}
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static int mtu_to_enum(u32 mtu)
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{
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int enum_mtu;
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switch (mtu) {
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case 4096:
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enum_mtu = IB_MTU_4096;
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break;
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case 2048:
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enum_mtu = IB_MTU_2048;
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break;
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case 1024:
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enum_mtu = IB_MTU_1024;
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break;
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case 512:
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enum_mtu = IB_MTU_512;
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break;
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case 256:
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enum_mtu = IB_MTU_256;
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break;
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default:
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enum_mtu = IB_MTU_2048;
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}
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return enum_mtu;
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}
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int qib_get_pmtu_from_attr(struct rvt_dev_info *rdi, struct rvt_qp *qp,
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struct ib_qp_attr *attr)
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{
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int mtu, pmtu, pidx = qp->port_num - 1;
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struct qib_ibdev *verbs_dev = container_of(rdi, struct qib_ibdev, rdi);
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struct qib_devdata *dd = container_of(verbs_dev, struct qib_devdata,
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verbs_dev);
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mtu = ib_mtu_enum_to_int(attr->path_mtu);
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if (mtu == -1)
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return -EINVAL;
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if (mtu > dd->pport[pidx].ibmtu)
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pmtu = mtu_to_enum(dd->pport[pidx].ibmtu);
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else
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pmtu = attr->path_mtu;
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return pmtu;
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}
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int qib_mtu_to_path_mtu(u32 mtu)
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{
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return mtu_to_enum(mtu);
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}
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u32 qib_mtu_from_qp(struct rvt_dev_info *rdi, struct rvt_qp *qp, u32 pmtu)
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{
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return ib_mtu_enum_to_int(pmtu);
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}
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void *qib_qp_priv_alloc(struct rvt_dev_info *rdi, struct rvt_qp *qp)
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{
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struct qib_qp_priv *priv;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return ERR_PTR(-ENOMEM);
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priv->owner = qp;
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priv->s_hdr = kzalloc(sizeof(*priv->s_hdr), GFP_KERNEL);
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if (!priv->s_hdr) {
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kfree(priv);
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return ERR_PTR(-ENOMEM);
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}
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init_waitqueue_head(&priv->wait_dma);
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INIT_WORK(&priv->s_work, _qib_do_send);
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INIT_LIST_HEAD(&priv->iowait);
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return priv;
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}
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void qib_qp_priv_free(struct rvt_dev_info *rdi, struct rvt_qp *qp)
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{
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struct qib_qp_priv *priv = qp->priv;
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kfree(priv->s_hdr);
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kfree(priv);
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}
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void qib_stop_send_queue(struct rvt_qp *qp)
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{
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struct qib_qp_priv *priv = qp->priv;
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cancel_work_sync(&priv->s_work);
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}
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void qib_quiesce_qp(struct rvt_qp *qp)
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{
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struct qib_qp_priv *priv = qp->priv;
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wait_event(priv->wait_dma, !atomic_read(&priv->s_dma_busy));
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if (priv->s_tx) {
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qib_put_txreq(priv->s_tx);
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priv->s_tx = NULL;
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}
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}
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void qib_flush_qp_waiters(struct rvt_qp *qp)
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{
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struct qib_qp_priv *priv = qp->priv;
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struct qib_ibdev *dev = to_idev(qp->ibqp.device);
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spin_lock(&dev->rdi.pending_lock);
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if (!list_empty(&priv->iowait))
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list_del_init(&priv->iowait);
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spin_unlock(&dev->rdi.pending_lock);
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}
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/**
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* qib_check_send_wqe - validate wr/wqe
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* @qp - The qp
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* @wqe - The built wqe
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* @call_send - Determine if the send should be posted or scheduled
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*
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* Returns 0 on success, -EINVAL on failure
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*/
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int qib_check_send_wqe(struct rvt_qp *qp,
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struct rvt_swqe *wqe, bool *call_send)
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{
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struct rvt_ah *ah;
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switch (qp->ibqp.qp_type) {
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case IB_QPT_RC:
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case IB_QPT_UC:
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if (wqe->length > 0x80000000U)
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return -EINVAL;
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if (wqe->length > qp->pmtu)
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*call_send = false;
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break;
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case IB_QPT_SMI:
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case IB_QPT_GSI:
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case IB_QPT_UD:
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ah = ibah_to_rvtah(wqe->ud_wr.ah);
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if (wqe->length > (1 << ah->log_pmtu))
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return -EINVAL;
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/* progress hint */
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*call_send = true;
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break;
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default:
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break;
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}
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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static const char * const qp_type_str[] = {
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"SMI", "GSI", "RC", "UC", "UD",
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};
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/**
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* qib_qp_iter_print - print information to seq_file
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* @s - the seq_file
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* @iter - the iterator
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*/
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void qib_qp_iter_print(struct seq_file *s, struct rvt_qp_iter *iter)
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{
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struct rvt_swqe *wqe;
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struct rvt_qp *qp = iter->qp;
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struct qib_qp_priv *priv = qp->priv;
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wqe = rvt_get_swqe_ptr(qp, qp->s_last);
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seq_printf(s,
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"N %d QP%u %s %u %u %u f=%x %u %u %u %u %u PSN %x %x %x %x %x (%u %u %u %u %u %u) QP%u LID %x\n",
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iter->n,
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qp->ibqp.qp_num,
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qp_type_str[qp->ibqp.qp_type],
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qp->state,
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wqe->wr.opcode,
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qp->s_hdrwords,
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qp->s_flags,
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atomic_read(&priv->s_dma_busy),
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!list_empty(&priv->iowait),
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qp->timeout,
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wqe->ssn,
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qp->s_lsn,
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qp->s_last_psn,
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qp->s_psn, qp->s_next_psn,
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qp->s_sending_psn, qp->s_sending_hpsn,
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qp->s_last, qp->s_acked, qp->s_cur,
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qp->s_tail, qp->s_head, qp->s_size,
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qp->remote_qpn,
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rdma_ah_get_dlid(&qp->remote_ah_attr));
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}
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#endif
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