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82b2f495fb
Secondary CPUs write to __boot_cpu_mode with caches disabled, and thus a cached value of __boot_cpu_mode may be incoherent with that in memory. This could lead to a failure to detect mismatched boot modes. This patch adds flushing to ensure that writes by secondaries to __boot_cpu_mode are made visible before we test against it. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Christoffer Dall <cdall@cs.columbia.edu> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
68 lines
2.1 KiB
C
68 lines
2.1 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM__VIRT_H
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#define __ASM__VIRT_H
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#define BOOT_CPU_MODE_EL2 (0x0e12b007)
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#ifndef __ASSEMBLY__
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#include <asm/cacheflush.h>
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/*
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* __boot_cpu_mode records what mode CPUs were booted in.
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* A correctly-implemented bootloader must start all CPUs in the same mode:
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* In this case, both 32bit halves of __boot_cpu_mode will contain the
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* same value (either 0 if booted in EL1, BOOT_CPU_MODE_EL2 if booted in EL2).
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*
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* Should the bootloader fail to do this, the two values will be different.
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* This allows the kernel to flag an error when the secondaries have come up.
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*/
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extern u32 __boot_cpu_mode[2];
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void __hyp_set_vectors(phys_addr_t phys_vector_base);
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phys_addr_t __hyp_get_vectors(void);
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static inline void sync_boot_mode(void)
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{
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/*
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* As secondaries write to __boot_cpu_mode with caches disabled, we
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* must flush the corresponding cache entries to ensure the visibility
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* of their writes.
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*/
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__flush_dcache_area(__boot_cpu_mode, sizeof(__boot_cpu_mode));
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}
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/* Reports the availability of HYP mode */
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static inline bool is_hyp_mode_available(void)
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{
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sync_boot_mode();
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return (__boot_cpu_mode[0] == BOOT_CPU_MODE_EL2 &&
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__boot_cpu_mode[1] == BOOT_CPU_MODE_EL2);
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}
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/* Check if the bootloader has booted CPUs in different modes */
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static inline bool is_hyp_mode_mismatched(void)
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{
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sync_boot_mode();
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return __boot_cpu_mode[0] != __boot_cpu_mode[1];
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}
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#endif /* __ASSEMBLY__ */
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#endif /* ! __ASM__VIRT_H */
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