mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 10:45:23 +07:00
2a81efb0de
Add compatible to gicv3 node to enable quirk required to restrict writing to GICR_WAKER register which is restricted on msm8996 SoC in Hypervisor. With this quirk MSM8996 can at least boot out of mainline, which can help community to work with boards based on MSM8996. Without this patch Qualcomm DB820c board reboots on mainline. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
1376 lines
31 KiB
Plaintext
1376 lines
31 KiB
Plaintext
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8996.h>
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#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
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#include <dt-bindings/clock/qcom,rpmcc.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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memory {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0 0 0>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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mba_region: mba@91500000 {
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reg = <0x0 0x91500000 0x0 0x200000>;
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no-map;
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};
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slpi_region: slpi@90b00000 {
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reg = <0x0 0x90b00000 0x0 0xa00000>;
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no-map;
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};
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venus_region: venus@90400000 {
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reg = <0x0 0x90400000 0x0 0x700000>;
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no-map;
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};
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adsp_region: adsp@8ea00000 {
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reg = <0x0 0x8ea00000 0x0 0x1a00000>;
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no-map;
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};
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mpss_region: mpss@88800000 {
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reg = <0x0 0x88800000 0x0 0x6200000>;
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no-map;
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};
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smem_mem: smem-mem@86000000 {
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reg = <0x0 0x86000000 0x0 0x200000>;
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no-map;
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};
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memory@85800000 {
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reg = <0x0 0x85800000 0x0 0x800000>;
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no-map;
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};
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memory@86200000 {
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reg = <0x0 0x86200000 0x0 0x2600000>;
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no-map;
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};
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rmtfs@86700000 {
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compatible = "qcom,rmtfs-mem";
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size = <0x0 0x200000>;
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alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
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no-map;
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qcom,client-id = <1>;
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qcom,vmid = <15>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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CPU3: cpu@101 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x101>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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};
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};
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};
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thermal-zones {
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cpu-thermal0 {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 3>;
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trips {
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cpu_alert0: trip0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit0: trip1 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu-thermal1 {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 5>;
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trips {
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cpu_alert1: trip0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit1: trip1 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu-thermal2 {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 8>;
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trips {
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cpu_alert2: trip0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit2: trip1 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu-thermal3 {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 10>;
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trips {
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cpu_alert3: trip0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit3: trip1 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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clocks {
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xo_board: xo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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clock-output-names = "xo_board";
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32764>;
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clock-output-names = "sleep_clk";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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firmware {
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scm {
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compatible = "qcom,scm-msm8996";
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qcom,dload-mode = <&tcsr 0x13000>;
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};
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_regs 0 0x1000>;
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#hwlock-cells = <1>;
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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rpm-glink {
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compatible = "qcom,glink-rpm";
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interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
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qcom,rpm-msg-ram = <&rpm_msg_ram>;
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mboxes = <&apcs_glb 0>;
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rpm_requests {
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compatible = "qcom,rpm-msm8996";
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qcom,glink-channels = "rpm_requests";
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rpmcc: qcom,rpmcc {
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compatible = "qcom,rpmcc-msm8996";
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#clock-cells = <1>;
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};
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pm8994-regulators {
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compatible = "qcom,rpm-pm8994-regulators";
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pm8994_s1: s1 {};
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pm8994_s2: s2 {};
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pm8994_s3: s3 {};
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pm8994_s4: s4 {};
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pm8994_s5: s5 {};
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pm8994_s6: s6 {};
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pm8994_s7: s7 {};
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pm8994_s8: s8 {};
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pm8994_s9: s9 {};
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pm8994_s10: s10 {};
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pm8994_s11: s11 {};
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pm8994_s12: s12 {};
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pm8994_l1: l1 {};
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pm8994_l2: l2 {};
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pm8994_l3: l3 {};
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pm8994_l4: l4 {};
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pm8994_l5: l5 {};
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pm8994_l6: l6 {};
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pm8994_l7: l7 {};
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pm8994_l8: l8 {};
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pm8994_l9: l9 {};
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pm8994_l10: l10 {};
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pm8994_l11: l11 {};
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pm8994_l12: l12 {};
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pm8994_l13: l13 {};
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pm8994_l14: l14 {};
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pm8994_l15: l15 {};
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pm8994_l16: l16 {};
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pm8994_l17: l17 {};
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pm8994_l18: l18 {};
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pm8994_l19: l19 {};
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pm8994_l20: l20 {};
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pm8994_l21: l21 {};
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pm8994_l22: l22 {};
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pm8994_l23: l23 {};
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pm8994_l24: l24 {};
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pm8994_l25: l25 {};
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pm8994_l26: l26 {};
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pm8994_l27: l27 {};
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pm8994_l28: l28 {};
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pm8994_l29: l29 {};
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pm8994_l30: l30 {};
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pm8994_l31: l31 {};
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pm8994_l32: l32 {};
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};
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};
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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rpm_msg_ram: memory@68000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0x68000 0x6000>;
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};
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rng: rng@83000 {
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compatible = "qcom,prng-ee";
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reg = <0x00083000 0x1000>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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};
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tcsr_mutex_regs: syscon@740000 {
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compatible = "syscon";
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reg = <0x740000 0x20000>;
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};
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tsens0: thermal-sensor@4a9000 {
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compatible = "qcom,msm8996-tsens";
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reg = <0x4a9000 0x1000>, /* TM */
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<0x4a8000 0x1000>; /* SROT */
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#qcom,sensors = <13>;
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#thermal-sensor-cells = <1>;
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};
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tsens1: thermal-sensor@4ad000 {
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compatible = "qcom,msm8996-tsens";
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reg = <0x4ad000 0x1000>, /* TM */
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<0x4ac000 0x1000>; /* SROT */
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#qcom,sensors = <8>;
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#thermal-sensor-cells = <1>;
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};
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tcsr: syscon@7a0000 {
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compatible = "qcom,tcsr-msm8996", "syscon";
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reg = <0x7a0000 0x18000>;
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};
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intc: interrupt-controller@9bc0000 {
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compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x40000>;
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reg = <0x09bc0000 0x10000>,
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<0x09c00000 0x100000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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apcs_glb: mailbox@9820000 {
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compatible = "qcom,msm8996-apcs-hmss-global";
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reg = <0x9820000 0x1000>;
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#mbox-cells = <1>;
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};
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gcc: clock-controller@300000 {
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compatible = "qcom,gcc-msm8996";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0x300000 0x90000>;
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};
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kryocc: clock-controller@6400000 {
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compatible = "qcom,apcc-msm8996";
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reg = <0x6400000 0x90000>;
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#clock-cells = <1>;
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};
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blsp1_uart1: serial@7570000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x07570000 0x1000>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_spi0: spi@7575000 {
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x07575000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp1_spi0_default>;
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pinctrl-1 = <&blsp1_spi0_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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blsp2_i2c0: i2c@75b5000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x075b5000 0x1000>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_AHB_CLK>,
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<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp2_i2c0_default>;
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pinctrl-1 = <&blsp2_i2c0_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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blsp2_uart1: serial@75b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x75b0000 0x1000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp2_i2c1: i2c@75b6000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x075b6000 0x1000>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_AHB_CLK>,
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<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp2_i2c1_default>;
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pinctrl-1 = <&blsp2_i2c1_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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blsp2_uart2: serial@75b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x075b1000 0x1000>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_i2c2: i2c@7577000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x07577000 0x1000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&blsp1_i2c2_default>;
|
|
pinctrl-1 = <&blsp1_i2c2_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
blsp2_spi5: spi@75ba000{
|
|
compatible = "qcom,spi-qup-v2.2.1";
|
|
reg = <0x075ba000 0x600>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
|
|
<&gcc GCC_BLSP2_AHB_CLK>;
|
|
clock-names = "core", "iface";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&blsp2_spi5_default>;
|
|
pinctrl-1 = <&blsp2_spi5_sleep>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhc2: sdhci@74a4900 {
|
|
status = "disabled";
|
|
compatible = "qcom,sdhci-msm-v4";
|
|
reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
|
|
reg-names = "hc_mem", "core_mem";
|
|
|
|
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 221 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
clock-names = "iface", "core", "xo";
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&gcc GCC_SDCC2_APPS_CLK>,
|
|
<&xo_board>;
|
|
bus-width = <4>;
|
|
};
|
|
|
|
msmgpio: pinctrl@1010000 {
|
|
compatible = "qcom,msm8996-pinctrl";
|
|
reg = <0x01010000 0x300000>;
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
timer@9840000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x09840000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@9850000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x09850000 0x1000>,
|
|
<0x09860000 0x1000>;
|
|
};
|
|
|
|
frame@9870000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x09870000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@9880000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x09880000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@9890000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x09890000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@98a0000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x098a0000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@98b0000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x098b0000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@98c0000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x098c0000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
spmi_bus: qcom,spmi@400f000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x400f000 0x1000>,
|
|
<0x4400000 0x800000>,
|
|
<0x4c00000 0x800000>,
|
|
<0x5800000 0x200000>,
|
|
<0x400a000 0x002100>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
};
|
|
|
|
ufsphy: phy@627000 {
|
|
compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
|
|
reg = <0x627000 0xda8>;
|
|
reg-names = "phy_mem";
|
|
#phy-cells = <0>;
|
|
|
|
vdda-phy-supply = <&pm8994_l28>;
|
|
vdda-pll-supply = <&pm8994_l12>;
|
|
|
|
vdda-phy-max-microamp = <18380>;
|
|
vdda-pll-max-microamp = <9440>;
|
|
|
|
vddp-ref-clk-supply = <&pm8994_l25>;
|
|
vddp-ref-clk-max-microamp = <100>;
|
|
vddp-ref-clk-always-on;
|
|
|
|
clock-names = "ref_clk_src", "ref_clk";
|
|
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
|
|
<&gcc GCC_UFS_CLKREF_CLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ufshc@624000 {
|
|
compatible = "qcom,ufshc";
|
|
reg = <0x624000 0x2500>;
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
phys = <&ufsphy>;
|
|
phy-names = "ufsphy";
|
|
|
|
vcc-supply = <&pm8994_l20>;
|
|
vccq-supply = <&pm8994_l25>;
|
|
vccq2-supply = <&pm8994_s4>;
|
|
|
|
vcc-max-microamp = <600000>;
|
|
vccq-max-microamp = <450000>;
|
|
vccq2-max-microamp = <450000>;
|
|
|
|
power-domains = <&gcc UFS_GDSC>;
|
|
|
|
clock-names =
|
|
"core_clk_src",
|
|
"core_clk",
|
|
"bus_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro_src",
|
|
"core_clk_unipro",
|
|
"core_clk_ice",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk";
|
|
clocks =
|
|
<&gcc UFS_AXI_CLK_SRC>,
|
|
<&gcc GCC_UFS_AXI_CLK>,
|
|
<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
|
|
<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
|
|
<&gcc GCC_UFS_AHB_CLK>,
|
|
<&gcc UFS_ICE_CORE_CLK_SRC>,
|
|
<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
|
|
<&gcc GCC_UFS_ICE_CORE_CLK>,
|
|
<&rpmcc RPM_SMD_LN_BB_CLK>,
|
|
<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
|
|
freq-table-hz =
|
|
<100000000 200000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<150000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>;
|
|
|
|
lanes-per-direction = <1>;
|
|
status = "disabled";
|
|
|
|
ufs_variant {
|
|
compatible = "qcom,ufs_variant";
|
|
};
|
|
};
|
|
|
|
mmcc: clock-controller@8c0000 {
|
|
compatible = "qcom,mmcc-msm8996";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
reg = <0x8c0000 0x40000>;
|
|
assigned-clocks = <&mmcc MMPLL9_PLL>,
|
|
<&mmcc MMPLL1_PLL>,
|
|
<&mmcc MMPLL3_PLL>,
|
|
<&mmcc MMPLL4_PLL>,
|
|
<&mmcc MMPLL5_PLL>;
|
|
assigned-clock-rates = <624000000>,
|
|
<810000000>,
|
|
<980000000>,
|
|
<960000000>,
|
|
<825000000>;
|
|
};
|
|
|
|
qfprom@74000 {
|
|
compatible = "qcom,qfprom";
|
|
reg = <0x74000 0x8ff>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
qusb2p_hstx_trim: hstx_trim@24e {
|
|
reg = <0x24e 0x2>;
|
|
bits = <5 4>;
|
|
};
|
|
|
|
qusb2s_hstx_trim: hstx_trim@24f {
|
|
reg = <0x24f 0x1>;
|
|
bits = <1 4>;
|
|
};
|
|
};
|
|
|
|
phy@34000 {
|
|
compatible = "qcom,msm8996-qmp-pcie-phy";
|
|
reg = <0x34000 0x488>;
|
|
#clock-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
|
|
<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_CLKREF_CLK>;
|
|
clock-names = "aux", "cfg_ahb", "ref";
|
|
|
|
vdda-phy-supply = <&pm8994_l28>;
|
|
vdda-pll-supply = <&pm8994_l12>;
|
|
|
|
resets = <&gcc GCC_PCIE_PHY_BCR>,
|
|
<&gcc GCC_PCIE_PHY_COM_BCR>,
|
|
<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
|
|
reset-names = "phy", "common", "cfg";
|
|
status = "disabled";
|
|
|
|
pciephy_0: lane@35000 {
|
|
reg = <0x035000 0x130>,
|
|
<0x035200 0x200>,
|
|
<0x035400 0x1dc>;
|
|
#phy-cells = <0>;
|
|
|
|
clock-output-names = "pcie_0_pipe_clk_src";
|
|
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
|
|
clock-names = "pipe0";
|
|
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
|
|
reset-names = "lane0";
|
|
};
|
|
|
|
pciephy_1: lane@36000 {
|
|
reg = <0x036000 0x130>,
|
|
<0x036200 0x200>,
|
|
<0x036400 0x1dc>;
|
|
#phy-cells = <0>;
|
|
|
|
clock-output-names = "pcie_1_pipe_clk_src";
|
|
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
|
|
clock-names = "pipe1";
|
|
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
|
|
reset-names = "lane1";
|
|
};
|
|
|
|
pciephy_2: lane@37000 {
|
|
reg = <0x037000 0x130>,
|
|
<0x037200 0x200>,
|
|
<0x037400 0x1dc>;
|
|
#phy-cells = <0>;
|
|
|
|
clock-output-names = "pcie_2_pipe_clk_src";
|
|
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
|
|
clock-names = "pipe2";
|
|
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
|
|
reset-names = "lane2";
|
|
};
|
|
};
|
|
|
|
phy@7410000 {
|
|
compatible = "qcom,msm8996-qmp-usb3-phy";
|
|
reg = <0x7410000 0x1c4>;
|
|
#clock-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
|
|
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
|
|
<&gcc GCC_USB3_CLKREF_CLK>;
|
|
clock-names = "aux", "cfg_ahb", "ref";
|
|
|
|
vdda-phy-supply = <&pm8994_l28>;
|
|
vdda-pll-supply = <&pm8994_l12>;
|
|
|
|
resets = <&gcc GCC_USB3_PHY_BCR>,
|
|
<&gcc GCC_USB3PHY_PHY_BCR>;
|
|
reset-names = "phy", "common";
|
|
status = "disabled";
|
|
|
|
ssusb_phy_0: lane@7410200 {
|
|
reg = <0x7410200 0x200>,
|
|
<0x7410400 0x130>,
|
|
<0x7410600 0x1a8>;
|
|
#phy-cells = <0>;
|
|
|
|
clock-output-names = "usb3_phy_pipe_clk_src";
|
|
clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
|
|
clock-names = "pipe0";
|
|
};
|
|
};
|
|
|
|
hsusb_phy1: phy@7411000 {
|
|
compatible = "qcom,msm8996-qusb2-phy";
|
|
reg = <0x7411000 0x180>;
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
|
|
<&gcc GCC_RX1_USB2_CLKREF_CLK>;
|
|
clock-names = "cfg_ahb", "ref";
|
|
|
|
vdda-pll-supply = <&pm8994_l12>;
|
|
vdda-phy-dpdm-supply = <&pm8994_l24>;
|
|
|
|
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
|
nvmem-cells = <&qusb2p_hstx_trim>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hsusb_phy2: phy@7412000 {
|
|
compatible = "qcom,msm8996-qusb2-phy";
|
|
reg = <0x7412000 0x180>;
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
|
|
<&gcc GCC_RX2_USB2_CLKREF_CLK>;
|
|
clock-names = "cfg_ahb", "ref";
|
|
|
|
vdda-pll-supply = <&pm8994_l12>;
|
|
vdda-phy-dpdm-supply = <&pm8994_l24>;
|
|
|
|
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
|
|
nvmem-cells = <&qusb2s_hstx_trim>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2: usb@76f8800 {
|
|
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
|
|
reg = <0x76f8800 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
|
|
<&gcc GCC_USB20_MASTER_CLK>,
|
|
<&gcc GCC_USB20_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB20_SLEEP_CLK>,
|
|
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
|
|
|
|
assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB20_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <60000000>;
|
|
|
|
power-domains = <&gcc USB30_GDSC>;
|
|
status = "disabled";
|
|
|
|
dwc3@7600000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x7600000 0xcc00>;
|
|
interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&hsusb_phy2>;
|
|
phy-names = "usb2-phy";
|
|
};
|
|
};
|
|
|
|
usb3: usb@6af8800 {
|
|
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
|
|
reg = <0x6af8800 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
|
|
<&gcc GCC_USB30_MASTER_CLK>,
|
|
<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
|
|
<&gcc GCC_USB30_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_SLEEP_CLK>,
|
|
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <120000000>;
|
|
|
|
power-domains = <&gcc USB30_GDSC>;
|
|
status = "disabled";
|
|
|
|
dwc3@6a00000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x6a00000 0xcc00>;
|
|
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&hsusb_phy1>, <&ssusb_phy_0>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
};
|
|
};
|
|
|
|
vfe_smmu: arm,smmu@da0000 {
|
|
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
|
|
reg = <0xda0000 0x10000>;
|
|
|
|
#global-interrupts = <1>;
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
|
|
clocks = <&mmcc SMMU_VFE_AHB_CLK>,
|
|
<&mmcc SMMU_VFE_AXI_CLK>;
|
|
clock-names = "iface",
|
|
"bus";
|
|
#iommu-cells = <1>;
|
|
status = "ok";
|
|
};
|
|
|
|
camss: camss@a00000 {
|
|
compatible = "qcom,msm8996-camss";
|
|
reg = <0xa34000 0x1000>,
|
|
<0xa00030 0x4>,
|
|
<0xa35000 0x1000>,
|
|
<0xa00038 0x4>,
|
|
<0xa36000 0x1000>,
|
|
<0xa00040 0x4>,
|
|
<0xa30000 0x100>,
|
|
<0xa30400 0x100>,
|
|
<0xa30800 0x100>,
|
|
<0xa30c00 0x100>,
|
|
<0xa31000 0x500>,
|
|
<0xa00020 0x10>,
|
|
<0xa10000 0x1000>,
|
|
<0xa14000 0x1000>;
|
|
reg-names = "csiphy0",
|
|
"csiphy0_clk_mux",
|
|
"csiphy1",
|
|
"csiphy1_clk_mux",
|
|
"csiphy2",
|
|
"csiphy2_clk_mux",
|
|
"csid0",
|
|
"csid1",
|
|
"csid2",
|
|
"csid3",
|
|
"ispif",
|
|
"csi_clk_mux",
|
|
"vfe0",
|
|
"vfe1";
|
|
interrupts = <GIC_SPI 78 0>,
|
|
<GIC_SPI 79 0>,
|
|
<GIC_SPI 80 0>,
|
|
<GIC_SPI 296 0>,
|
|
<GIC_SPI 297 0>,
|
|
<GIC_SPI 298 0>,
|
|
<GIC_SPI 299 0>,
|
|
<GIC_SPI 309 0>,
|
|
<GIC_SPI 314 0>,
|
|
<GIC_SPI 315 0>;
|
|
interrupt-names = "csiphy0",
|
|
"csiphy1",
|
|
"csiphy2",
|
|
"csid0",
|
|
"csid1",
|
|
"csid2",
|
|
"csid3",
|
|
"ispif",
|
|
"vfe0",
|
|
"vfe1";
|
|
power-domains = <&mmcc VFE0_GDSC>;
|
|
clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
|
|
<&mmcc CAMSS_ISPIF_AHB_CLK>,
|
|
<&mmcc CAMSS_CSI0PHYTIMER_CLK>,
|
|
<&mmcc CAMSS_CSI1PHYTIMER_CLK>,
|
|
<&mmcc CAMSS_CSI2PHYTIMER_CLK>,
|
|
<&mmcc CAMSS_CSI0_AHB_CLK>,
|
|
<&mmcc CAMSS_CSI0_CLK>,
|
|
<&mmcc CAMSS_CSI0PHY_CLK>,
|
|
<&mmcc CAMSS_CSI0PIX_CLK>,
|
|
<&mmcc CAMSS_CSI0RDI_CLK>,
|
|
<&mmcc CAMSS_CSI1_AHB_CLK>,
|
|
<&mmcc CAMSS_CSI1_CLK>,
|
|
<&mmcc CAMSS_CSI1PHY_CLK>,
|
|
<&mmcc CAMSS_CSI1PIX_CLK>,
|
|
<&mmcc CAMSS_CSI1RDI_CLK>,
|
|
<&mmcc CAMSS_CSI2_AHB_CLK>,
|
|
<&mmcc CAMSS_CSI2_CLK>,
|
|
<&mmcc CAMSS_CSI2PHY_CLK>,
|
|
<&mmcc CAMSS_CSI2PIX_CLK>,
|
|
<&mmcc CAMSS_CSI2RDI_CLK>,
|
|
<&mmcc CAMSS_CSI3_AHB_CLK>,
|
|
<&mmcc CAMSS_CSI3_CLK>,
|
|
<&mmcc CAMSS_CSI3PHY_CLK>,
|
|
<&mmcc CAMSS_CSI3PIX_CLK>,
|
|
<&mmcc CAMSS_CSI3RDI_CLK>,
|
|
<&mmcc CAMSS_AHB_CLK>,
|
|
<&mmcc CAMSS_VFE0_CLK>,
|
|
<&mmcc CAMSS_CSI_VFE0_CLK>,
|
|
<&mmcc CAMSS_VFE0_AHB_CLK>,
|
|
<&mmcc CAMSS_VFE0_STREAM_CLK>,
|
|
<&mmcc CAMSS_VFE1_CLK>,
|
|
<&mmcc CAMSS_CSI_VFE1_CLK>,
|
|
<&mmcc CAMSS_VFE1_AHB_CLK>,
|
|
<&mmcc CAMSS_VFE1_STREAM_CLK>,
|
|
<&mmcc CAMSS_VFE_AHB_CLK>,
|
|
<&mmcc CAMSS_VFE_AXI_CLK>;
|
|
clock-names = "top_ahb",
|
|
"ispif_ahb",
|
|
"csiphy0_timer",
|
|
"csiphy1_timer",
|
|
"csiphy2_timer",
|
|
"csi0_ahb",
|
|
"csi0",
|
|
"csi0_phy",
|
|
"csi0_pix",
|
|
"csi0_rdi",
|
|
"csi1_ahb",
|
|
"csi1",
|
|
"csi1_phy",
|
|
"csi1_pix",
|
|
"csi1_rdi",
|
|
"csi2_ahb",
|
|
"csi2",
|
|
"csi2_phy",
|
|
"csi2_pix",
|
|
"csi2_rdi",
|
|
"csi3_ahb",
|
|
"csi3",
|
|
"csi3_phy",
|
|
"csi3_pix",
|
|
"csi3_rdi",
|
|
"ahb",
|
|
"vfe0",
|
|
"csi_vfe0",
|
|
"vfe0_ahb",
|
|
"vfe0_stream",
|
|
"vfe1",
|
|
"csi_vfe1",
|
|
"vfe1_ahb",
|
|
"vfe1_stream",
|
|
"vfe_ahb",
|
|
"vfe_axi";
|
|
vdda-supply = <&pm8994_l2>;
|
|
iommus = <&vfe_smmu 0>,
|
|
<&vfe_smmu 1>,
|
|
<&vfe_smmu 2>,
|
|
<&vfe_smmu 3>;
|
|
status = "disabled";
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
agnoc@0 {
|
|
power-domains = <&gcc AGGRE0_NOC_GDSC>;
|
|
compatible = "simple-pm-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
pcie0: pcie@600000 {
|
|
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
|
|
status = "disabled";
|
|
power-domains = <&gcc PCIE0_GDSC>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
|
|
reg = <0x00600000 0x2000>,
|
|
<0x0c000000 0xf1d>,
|
|
<0x0c000f20 0xa8>,
|
|
<0x0c100000 0x100000>;
|
|
reg-names = "parf", "dbi", "elbi","config";
|
|
|
|
phys = <&pciephy_0>;
|
|
phy-names = "pciephy";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
|
|
|
|
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
|
|
pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
|
|
|
|
|
|
vdda-supply = <&pm8994_l28>;
|
|
|
|
linux,pci-domain = <0>;
|
|
|
|
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
|
<&gcc GCC_PCIE_0_AUX_CLK>,
|
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
|
|
|
|
clock-names = "pipe",
|
|
"aux",
|
|
"cfg",
|
|
"bus_master",
|
|
"bus_slave";
|
|
|
|
};
|
|
|
|
pcie1: pcie@608000 {
|
|
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
|
|
power-domains = <&gcc PCIE1_GDSC>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
|
|
status = "disabled";
|
|
|
|
reg = <0x00608000 0x2000>,
|
|
<0x0d000000 0xf1d>,
|
|
<0x0d000f20 0xa8>,
|
|
<0x0d100000 0x100000>;
|
|
|
|
reg-names = "parf", "dbi", "elbi","config";
|
|
|
|
phys = <&pciephy_1>;
|
|
phy-names = "pciephy";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
|
|
|
|
interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
|
|
pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
|
|
|
|
|
|
vdda-supply = <&pm8994_l28>;
|
|
linux,pci-domain = <1>;
|
|
|
|
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
|
|
<&gcc GCC_PCIE_1_AUX_CLK>,
|
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
|
|
|
|
clock-names = "pipe",
|
|
"aux",
|
|
"cfg",
|
|
"bus_master",
|
|
"bus_slave";
|
|
};
|
|
|
|
pcie2: pcie@610000 {
|
|
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
|
|
power-domains = <&gcc PCIE2_GDSC>;
|
|
bus-range = <0x00 0xff>;
|
|
num-lanes = <1>;
|
|
status = "disabled";
|
|
reg = <0x00610000 0x2000>,
|
|
<0x0e000000 0xf1d>,
|
|
<0x0e000f20 0xa8>,
|
|
<0x0e100000 0x100000>;
|
|
|
|
reg-names = "parf", "dbi", "elbi","config";
|
|
|
|
phys = <&pciephy_2>;
|
|
phy-names = "pciephy";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
|
|
|
|
device_type = "pci";
|
|
|
|
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
|
|
<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
|
|
<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|
<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
|
|
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
|
|
pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
|
|
|
|
vdda-supply = <&pm8994_l28>;
|
|
|
|
linux,pci-domain = <2>;
|
|
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
|
|
<&gcc GCC_PCIE_2_AUX_CLK>,
|
|
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
|
|
|
|
clock-names = "pipe",
|
|
"aux",
|
|
"cfg",
|
|
"bus_master",
|
|
"bus_slave";
|
|
};
|
|
};
|
|
};
|
|
|
|
adsp-pil {
|
|
compatible = "qcom,msm8996-adsp-pil";
|
|
|
|
interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready",
|
|
"handover", "stop-ack";
|
|
|
|
clocks = <&xo_board>;
|
|
clock-names = "xo";
|
|
|
|
memory-region = <&adsp_region>;
|
|
|
|
qcom,smem-states = <&adsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
smd-edge {
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "lpass";
|
|
mboxes = <&apcs_glb 8>;
|
|
qcom,smd-edge = <1>;
|
|
qcom,remote-pid = <2>;
|
|
};
|
|
};
|
|
|
|
adsp-smp2p {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <443>, <429>;
|
|
|
|
interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
mboxes = <&apcs_glb 10>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
|
|
adsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
adsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
modem-smp2p {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
|
|
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
mboxes = <&apcs_glb 14>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
modem_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
modem_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-slpi {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <481>, <430>;
|
|
|
|
interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
mboxes = <&apcs_glb 26>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <3>;
|
|
|
|
slpi_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
slpi_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
};
|
|
|
|
};
|
|
#include "msm8996-pins.dtsi"
|