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9d2ee0a60b
On brcmnand controller v6.x and v7.x, the #WP pin is controlled through
the NAND_WP bit in CS_SELECT register.
The driver currently assumes that toggling the #WP pin is
instantaneously enabling/disabling write-protection, but it actually
takes some time to propagate the new state to the internal NAND chip
logic. This behavior is sometime causing data corruptions when an
erase/program operation is executed before write-protection has really
been disabled.
Fixes:
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.. | ||
bcm6368_nand.c | ||
bcm63138_nand.c | ||
brcmnand.c | ||
brcmnand.h | ||
brcmstb_nand.c | ||
iproc_nand.c | ||
Makefile |