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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6e4b3b4b66
The pincontroller uses the GRF and PMU syscons nowadays, so should not contain an address in its device node. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
294 lines
6.2 KiB
Plaintext
294 lines
6.2 KiB
Plaintext
/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3188-cru.h>
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#include "rk3xxx.dtsi"
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/ {
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compatible = "rockchip,rk3188";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "rockchip,rk3066-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x3>;
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};
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};
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sram: sram@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x8000>;
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smp-sram@0 {
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compatible = "rockchip,rk3066-smp-sram";
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reg = <0x0 0x50>;
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};
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};
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cru: clock-controller@20000000 {
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compatible = "rockchip,rk3188-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3188-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmu>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@0x2000a000 {
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compatible = "rockchip,rk3188-gpio-bank0";
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reg = <0x2000a000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@0x2003c000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003c000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@2003e000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003e000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio3@20080000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20080000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_up: pcfg_pull_up {
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bias-pull-up;
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};
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pcfg_pull_down: pcfg_pull_down {
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bias-pull-down;
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};
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pcfg_pull_none: pcfg_pull_none {
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bias-disable;
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};
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uart0 {
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uart0_xfer: uart0-xfer {
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rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart0_cts: uart0-cts {
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rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart0_rts: uart0-rts {
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rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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uart1 {
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uart1_xfer: uart1-xfer {
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rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart1_cts: uart1-cts {
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rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart1_rts: uart1-rts {
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rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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uart2 {
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uart2_xfer: uart2-xfer {
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rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
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};
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/* no rts / cts for uart2 */
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};
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uart3 {
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uart3_xfer: uart3-xfer {
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rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart3_cts: uart3-cts {
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rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart3_rts: uart3-rts {
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rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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sd0 {
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sd0_clk: sd0-clk {
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rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_cmd: sd0-cmd {
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rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_cd: sd0-cd {
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rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_wp: sd0-wp {
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rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_pwr: sd0-pwr {
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rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_bus1: sd0-bus-width1 {
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rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_bus4: sd0-bus-width4 {
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rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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sd1 {
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sd1_clk: sd1-clk {
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rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd1_cmd: sd1-cmd {
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rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd1_cd: sd1-cd {
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rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd1_wp: sd1-wp {
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rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd1_bus1: sd1-bus-width1 {
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rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd1_bus4: sd1-bus-width4 {
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rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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};
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};
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&global_timer {
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interrupts = <GIC_PPI 11 0xf04>;
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};
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&local_timer {
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interrupts = <GIC_PPI 13 0xf04>;
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer>;
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_xfer>;
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};
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