mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 15:57:01 +07:00
1839533f69
Add clkctrl nodes for DRA7 SoC. These are going to be acting as replacement for part of the existing clock data and the existing clkctrl hooks under hwmod data. This patch also removes any obsolete clock nodes, and reroutes all users for these to use the new clkctrl clocks instead. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
570 lines
13 KiB
Plaintext
570 lines
13 KiB
Plaintext
/*
|
|
* Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
/dts-v1/;
|
|
|
|
#include "dra72x.dtsi"
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/clk/ti-dra7-atl.h>
|
|
|
|
/ {
|
|
compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
|
|
|
|
aliases {
|
|
display0 = &hdmi0;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = &uart1;
|
|
};
|
|
|
|
evm_12v0: fixedregulator-evm12v0 {
|
|
/* main supply */
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "evm_12v0";
|
|
regulator-min-microvolt = <12000000>;
|
|
regulator-max-microvolt = <12000000>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
evm_5v0: fixedregulator-evm5v0 {
|
|
/* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
|
|
/* Output 1 of LM5140QRWGTQ1 on dra71-evm */
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "evm_5v0";
|
|
regulator-min-microvolt = <5000000>;
|
|
regulator-max-microvolt = <5000000>;
|
|
vin-supply = <&evm_12v0>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
vsys_3v3: fixedregulator-vsys3v3 {
|
|
/* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
|
|
/* Output 2 of LM5140QRWGTQ1 on dra71-evm */
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "vsys_3v3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
vin-supply = <&evm_12v0>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
evm_3v3_sw: fixedregulator-evm_3v3 {
|
|
/* TPS22965DSG */
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "evm_3v3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
vin-supply = <&vsys_3v3>;
|
|
regulator-always-on;
|
|
regulator-boot-on;
|
|
};
|
|
|
|
aic_dvdd: fixedregulator-aic_dvdd {
|
|
/* TPS77018DBVT */
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "aic_dvdd";
|
|
vin-supply = <&evm_3v3_sw>;
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
};
|
|
|
|
evm_3v3_sd: fixedregulator-sd {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "evm_3v3_sd";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
vin-supply = <&evm_3v3_sw>;
|
|
enable-active-high;
|
|
gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
extcon_usb1: extcon_usb1 {
|
|
compatible = "linux,extcon-usb-gpio";
|
|
id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
extcon_usb2: extcon_usb2 {
|
|
compatible = "linux,extcon-usb-gpio";
|
|
id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
hdmi0: connector {
|
|
compatible = "hdmi-connector";
|
|
label = "hdmi";
|
|
|
|
type = "a";
|
|
|
|
port {
|
|
hdmi_connector_in: endpoint {
|
|
remote-endpoint = <&tpd12s015_out>;
|
|
};
|
|
};
|
|
};
|
|
|
|
tpd12s015: encoder {
|
|
compatible = "ti,tpd12s015";
|
|
|
|
gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
|
|
<&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
|
|
<&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
tpd12s015_in: endpoint {
|
|
remote-endpoint = <&hdmi_out>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
tpd12s015_out: endpoint {
|
|
remote-endpoint = <&hdmi_connector_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
sound0: sound0 {
|
|
compatible = "simple-audio-card";
|
|
simple-audio-card,name = "DRA7xx-EVM";
|
|
simple-audio-card,widgets =
|
|
"Headphone", "Headphone Jack",
|
|
"Line", "Line Out",
|
|
"Microphone", "Mic Jack",
|
|
"Line", "Line In";
|
|
simple-audio-card,routing =
|
|
"Headphone Jack", "HPLOUT",
|
|
"Headphone Jack", "HPROUT",
|
|
"Line Out", "LLOUT",
|
|
"Line Out", "RLOUT",
|
|
"MIC3L", "Mic Jack",
|
|
"MIC3R", "Mic Jack",
|
|
"Mic Jack", "Mic Bias",
|
|
"LINE1L", "Line In",
|
|
"LINE1R", "Line In";
|
|
simple-audio-card,format = "dsp_b";
|
|
simple-audio-card,bitclock-master = <&sound0_master>;
|
|
simple-audio-card,frame-master = <&sound0_master>;
|
|
simple-audio-card,bitclock-inversion;
|
|
|
|
sound0_master: simple-audio-card,cpu {
|
|
sound-dai = <&mcasp3>;
|
|
system-clock-frequency = <5644800>;
|
|
};
|
|
|
|
simple-audio-card,codec {
|
|
sound-dai = <&tlv320aic3106>;
|
|
clocks = <&atl_clkin2_ck>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&dra7_pmx_core {
|
|
mmc1_pins_default: mmc1_pins_default {
|
|
pinctrl-single,pins = <
|
|
DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
|
|
DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
|
|
DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
|
|
DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
|
|
DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
|
|
DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
|
|
DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
|
|
>;
|
|
};
|
|
|
|
mmc2_pins_default: mmc2_pins_default {
|
|
pinctrl-single,pins = <
|
|
DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
|
|
DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
|
|
DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
|
|
DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
|
|
DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
|
|
DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
|
|
DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
|
|
DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
|
|
DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
|
|
DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
|
|
>;
|
|
};
|
|
|
|
dcan1_pins_default: dcan1_pins_default {
|
|
pinctrl-single,pins = <
|
|
DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
|
|
DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
|
|
>;
|
|
};
|
|
|
|
dcan1_pins_sleep: dcan1_pins_sleep {
|
|
pinctrl-single,pins = <
|
|
DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
|
|
DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
|
|
>;
|
|
};
|
|
};
|
|
|
|
&i2c1 {
|
|
status = "okay";
|
|
clock-frequency = <400000>;
|
|
|
|
pcf_lcd: gpio@20 {
|
|
compatible = "nxp,pcf8575";
|
|
reg = <0x20>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pcf_gpio_21: gpio@21 {
|
|
compatible = "ti,pcf8575", "nxp,pcf8575";
|
|
reg = <0x21>;
|
|
lines-initial-states = <0x1408>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
tlv320aic3106: tlv320aic3106@19 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "ti,tlv320aic3106";
|
|
reg = <0x19>;
|
|
adc-settle-ms = <40>;
|
|
ai3x-micbias-vg = <1>; /* 2.0V */
|
|
status = "okay";
|
|
|
|
/* Regulators */
|
|
AVDD-supply = <&evm_3v3_sw>;
|
|
IOVDD-supply = <&evm_3v3_sw>;
|
|
DRVDD-supply = <&evm_3v3_sw>;
|
|
DVDD-supply = <&aic_dvdd>;
|
|
};
|
|
};
|
|
|
|
&i2c5 {
|
|
status = "okay";
|
|
clock-frequency = <400000>;
|
|
|
|
pcf_hdmi: pcf8575@26 {
|
|
compatible = "ti,pcf8575", "nxp,pcf8575";
|
|
reg = <0x26>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
/*
|
|
* initial state is used here to keep the mdio interface
|
|
* selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
|
|
* VIN2_S0 driven high otherwise Ethernet stops working
|
|
* VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
|
|
*/
|
|
lines-initial-states = <0x0f2b>;
|
|
|
|
p1 {
|
|
/* vin6_sel_s0: high: VIN6, low: audio */
|
|
gpio-hog;
|
|
gpios = <1 GPIO_ACTIVE_HIGH>;
|
|
output-low;
|
|
line-name = "vin6_sel_s0";
|
|
};
|
|
};
|
|
};
|
|
|
|
&uart1 {
|
|
status = "okay";
|
|
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&dra7_pmx_core 0x3e0>;
|
|
};
|
|
|
|
&elm {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpmc {
|
|
/*
|
|
* For the existing IOdelay configuration via U-Boot we don't
|
|
* support NAND on dra72-evm. Keep it disabled. Enabling it
|
|
* requires a different configuration by U-Boot.
|
|
*/
|
|
status = "disabled";
|
|
ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */
|
|
nand@0,0 {
|
|
/* To use NAND, DIP switch SW5 must be set like so:
|
|
* SW5.1 (NAND_SELn) = ON (LOW)
|
|
* SW5.9 (GPMC_WPN) = OFF (HIGH)
|
|
*/
|
|
compatible = "ti,omap2-nand";
|
|
reg = <0 0 4>; /* device IO registers */
|
|
interrupt-parent = <&gpmc>;
|
|
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
|
<1 IRQ_TYPE_NONE>; /* termcount */
|
|
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
|
|
ti,nand-xfer-type = "prefetch-dma";
|
|
ti,nand-ecc-opt = "bch8";
|
|
ti,elm-id = <&elm>;
|
|
nand-bus-width = <16>;
|
|
gpmc,device-width = <2>;
|
|
gpmc,sync-clk-ps = <0>;
|
|
gpmc,cs-on-ns = <0>;
|
|
gpmc,cs-rd-off-ns = <80>;
|
|
gpmc,cs-wr-off-ns = <80>;
|
|
gpmc,adv-on-ns = <0>;
|
|
gpmc,adv-rd-off-ns = <60>;
|
|
gpmc,adv-wr-off-ns = <60>;
|
|
gpmc,we-on-ns = <10>;
|
|
gpmc,we-off-ns = <50>;
|
|
gpmc,oe-on-ns = <4>;
|
|
gpmc,oe-off-ns = <40>;
|
|
gpmc,access-ns = <40>;
|
|
gpmc,wr-access-ns = <80>;
|
|
gpmc,rd-cycle-ns = <80>;
|
|
gpmc,wr-cycle-ns = <80>;
|
|
gpmc,bus-turnaround-ns = <0>;
|
|
gpmc,cycle2cycle-delay-ns = <0>;
|
|
gpmc,clk-activation-ns = <0>;
|
|
gpmc,wr-data-mux-bus-ns = <0>;
|
|
/* MTD partition table */
|
|
/* All SPL-* partitions are sized to minimal length
|
|
* which can be independently programmable. For
|
|
* NAND flash this is equal to size of erase-block */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
partition@0 {
|
|
label = "NAND.SPL";
|
|
reg = <0x00000000 0x000020000>;
|
|
};
|
|
partition@1 {
|
|
label = "NAND.SPL.backup1";
|
|
reg = <0x00020000 0x00020000>;
|
|
};
|
|
partition@2 {
|
|
label = "NAND.SPL.backup2";
|
|
reg = <0x00040000 0x00020000>;
|
|
};
|
|
partition@3 {
|
|
label = "NAND.SPL.backup3";
|
|
reg = <0x00060000 0x00020000>;
|
|
};
|
|
partition@4 {
|
|
label = "NAND.u-boot-spl-os";
|
|
reg = <0x00080000 0x00040000>;
|
|
};
|
|
partition@5 {
|
|
label = "NAND.u-boot";
|
|
reg = <0x000c0000 0x00100000>;
|
|
};
|
|
partition@6 {
|
|
label = "NAND.u-boot-env";
|
|
reg = <0x001c0000 0x00020000>;
|
|
};
|
|
partition@7 {
|
|
label = "NAND.u-boot-env.backup1";
|
|
reg = <0x001e0000 0x00020000>;
|
|
};
|
|
partition@8 {
|
|
label = "NAND.kernel";
|
|
reg = <0x00200000 0x00800000>;
|
|
};
|
|
partition@9 {
|
|
label = "NAND.file-system";
|
|
reg = <0x00a00000 0x0f600000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&omap_dwc3_1 {
|
|
extcon = <&extcon_usb1>;
|
|
};
|
|
|
|
&omap_dwc3_2 {
|
|
extcon = <&extcon_usb2>;
|
|
};
|
|
|
|
&usb1 {
|
|
dr_mode = "otg";
|
|
extcon = <&extcon_usb1>;
|
|
};
|
|
|
|
&usb2 {
|
|
dr_mode = "host";
|
|
};
|
|
|
|
&mmc1 {
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc1_pins_default>;
|
|
vmmc-supply = <&evm_3v3_sd>;
|
|
bus-width = <4>;
|
|
/*
|
|
* SDCD signal is not being used here - using the fact that GPIO mode
|
|
* is a viable alternative
|
|
*/
|
|
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
|
|
max-frequency = <192000000>;
|
|
};
|
|
|
|
&mmc2 {
|
|
/* SW5-3 in ON position */
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc2_pins_default>;
|
|
bus-width = <8>;
|
|
ti,non-removable;
|
|
max-frequency = <192000000>;
|
|
};
|
|
|
|
&mac {
|
|
status = "okay";
|
|
};
|
|
|
|
&dcan1 {
|
|
status = "ok";
|
|
pinctrl-names = "default", "sleep", "active";
|
|
pinctrl-0 = <&dcan1_pins_sleep>;
|
|
pinctrl-1 = <&dcan1_pins_sleep>;
|
|
pinctrl-2 = <&dcan1_pins_default>;
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
|
|
spi-max-frequency = <76800000>;
|
|
m25p80@0 {
|
|
compatible = "s25fl256s1";
|
|
spi-max-frequency = <76800000>;
|
|
reg = <0>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
/* MTD partition table.
|
|
* The ROM checks the first four physical blocks
|
|
* for a valid file to boot and the flash here is
|
|
* 64KiB block size.
|
|
*/
|
|
partition@0 {
|
|
label = "QSPI.SPL";
|
|
reg = <0x00000000 0x000010000>;
|
|
};
|
|
partition@1 {
|
|
label = "QSPI.SPL.backup1";
|
|
reg = <0x00010000 0x00010000>;
|
|
};
|
|
partition@2 {
|
|
label = "QSPI.SPL.backup2";
|
|
reg = <0x00020000 0x00010000>;
|
|
};
|
|
partition@3 {
|
|
label = "QSPI.SPL.backup3";
|
|
reg = <0x00030000 0x00010000>;
|
|
};
|
|
partition@4 {
|
|
label = "QSPI.u-boot";
|
|
reg = <0x00040000 0x00100000>;
|
|
};
|
|
partition@5 {
|
|
label = "QSPI.u-boot-spl-os";
|
|
reg = <0x00140000 0x00080000>;
|
|
};
|
|
partition@6 {
|
|
label = "QSPI.u-boot-env";
|
|
reg = <0x001c0000 0x00010000>;
|
|
};
|
|
partition@7 {
|
|
label = "QSPI.u-boot-env.backup1";
|
|
reg = <0x001d0000 0x0010000>;
|
|
};
|
|
partition@8 {
|
|
label = "QSPI.kernel";
|
|
reg = <0x001e0000 0x0800000>;
|
|
};
|
|
partition@9 {
|
|
label = "QSPI.file-system";
|
|
reg = <0x009e0000 0x01620000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&dss {
|
|
status = "ok";
|
|
};
|
|
|
|
&hdmi {
|
|
status = "ok";
|
|
|
|
port {
|
|
hdmi_out: endpoint {
|
|
remote-endpoint = <&tpd12s015_in>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&atl {
|
|
assigned-clocks = <&abe_dpll_sys_clk_mux>,
|
|
<&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
|
|
<&dpll_abe_ck>,
|
|
<&dpll_abe_m2x2_ck>,
|
|
<&atl_clkin2_ck>;
|
|
assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
|
|
assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
|
|
|
|
status = "okay";
|
|
|
|
atl2 {
|
|
bws = <DRA7_ATL_WS_MCASP2_FSX>;
|
|
aws = <DRA7_ATL_WS_MCASP3_FSX>;
|
|
};
|
|
};
|
|
|
|
&mcasp3 {
|
|
#sound-dai-cells = <0>;
|
|
|
|
assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
|
|
assigned-clock-parents = <&atl_clkin2_ck>;
|
|
|
|
status = "okay";
|
|
|
|
op-mode = <0>; /* MCASP_IIS_MODE */
|
|
tdm-slots = <2>;
|
|
/* 4 serializer */
|
|
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
|
1 2 0 0
|
|
>;
|
|
tx-num-evt = <32>;
|
|
rx-num-evt = <32>;
|
|
};
|
|
|
|
&mailbox5 {
|
|
status = "okay";
|
|
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
|
|
status = "okay";
|
|
};
|
|
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&mailbox6 {
|
|
status = "okay";
|
|
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&pcie1_rc {
|
|
status = "okay";
|
|
};
|