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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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141 lines
3.3 KiB
C
141 lines
3.3 KiB
C
/*
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* TLB flushing operations for SH with an MMU.
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/mm.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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unsigned int cpu = smp_processor_id();
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if (vma->vm_mm && cpu_context(cpu, vma->vm_mm) != NO_CONTEXT) {
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unsigned long flags;
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unsigned long asid;
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unsigned long saved_asid = MMU_NO_ASID;
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asid = cpu_asid(cpu, vma->vm_mm);
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page &= PAGE_MASK;
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local_irq_save(flags);
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if (vma->vm_mm != current->mm) {
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saved_asid = get_asid();
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set_asid(asid);
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}
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local_flush_tlb_one(asid, page);
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if (saved_asid != MMU_NO_ASID)
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set_asid(saved_asid);
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local_irq_restore(flags);
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}
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}
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void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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unsigned int cpu = smp_processor_id();
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if (cpu_context(cpu, mm) != NO_CONTEXT) {
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unsigned long flags;
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int size;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
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cpu_context(cpu, mm) = NO_CONTEXT;
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if (mm == current->mm)
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activate_context(mm, cpu);
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} else {
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unsigned long asid;
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unsigned long saved_asid = MMU_NO_ASID;
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asid = cpu_asid(cpu, mm);
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start &= PAGE_MASK;
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end += (PAGE_SIZE - 1);
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end &= PAGE_MASK;
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if (mm != current->mm) {
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saved_asid = get_asid();
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set_asid(asid);
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}
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while (start < end) {
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local_flush_tlb_one(asid, start);
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start += PAGE_SIZE;
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}
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if (saved_asid != MMU_NO_ASID)
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set_asid(saved_asid);
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}
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local_irq_restore(flags);
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}
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}
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned int cpu = smp_processor_id();
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unsigned long flags;
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int size;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
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local_flush_tlb_all();
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} else {
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unsigned long asid;
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unsigned long saved_asid = get_asid();
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asid = cpu_asid(cpu, &init_mm);
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start &= PAGE_MASK;
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end += (PAGE_SIZE - 1);
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end &= PAGE_MASK;
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set_asid(asid);
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while (start < end) {
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local_flush_tlb_one(asid, start);
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start += PAGE_SIZE;
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}
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set_asid(saved_asid);
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}
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local_irq_restore(flags);
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}
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void local_flush_tlb_mm(struct mm_struct *mm)
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{
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unsigned int cpu = smp_processor_id();
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/* Invalidate all TLB of this process. */
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/* Instead of invalidating each TLB, we get new MMU context. */
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if (cpu_context(cpu, mm) != NO_CONTEXT) {
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unsigned long flags;
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local_irq_save(flags);
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cpu_context(cpu, mm) = NO_CONTEXT;
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if (mm == current->mm)
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activate_context(mm, cpu);
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local_irq_restore(flags);
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}
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}
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void local_flush_tlb_all(void)
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{
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unsigned long flags, status;
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/*
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* Flush all the TLB.
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*
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* Write to the MMU control register's bit:
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* TF-bit for SH-3, TI-bit for SH-4.
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* It's same position, bit #2.
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*/
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local_irq_save(flags);
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status = ctrl_inl(MMUCR);
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status |= 0x04;
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ctrl_outl(status, MMUCR);
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ctrl_barrier();
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local_irq_restore(flags);
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}
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