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16ba0dc6ea
Added property for DMA configuration of the device. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
42 lines
1.6 KiB
Plaintext
42 lines
1.6 KiB
Plaintext
* AT91 SAMA5D2 Analog to Digital Converter (ADC)
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Required properties:
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- compatible: Should be "atmel,sama5d2-adc".
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- reg: Should contain ADC registers location and length.
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- interrupts: Should contain the IRQ line for the ADC.
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- clocks: phandle to device clock.
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- clock-names: Must be "adc_clk".
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- vref-supply: Supply used as reference for conversions.
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- vddana-supply: Supply for the adc device.
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- atmel,min-sample-rate-hz: Minimum sampling rate, it depends on SoC.
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- atmel,max-sample-rate-hz: Maximum sampling rate, it depends on SoC.
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- atmel,startup-time-ms: Startup time expressed in ms, it depends on SoC.
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- atmel,trigger-edge-type: One of possible edge types for the ADTRG hardware
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trigger pin. When the specific edge type is detected, the conversion will
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start. Possible values are rising, falling, or both.
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This property uses the IRQ edge types values: IRQ_TYPE_EDGE_RISING ,
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IRQ_TYPE_EDGE_FALLING or IRQ_TYPE_EDGE_BOTH
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Optional properties:
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- dmas: Phandle to dma channel for the ADC.
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- dma-names: Must be "rx" when dmas property is being used.
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See ../../dma/dma.txt for details.
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Example:
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adc: adc@fc030000 {
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compatible = "atmel,sama5d2-adc";
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reg = <0xfc030000 0x100>;
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interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
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clocks = <&adc_clk>;
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clock-names = "adc_clk";
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atmel,min-sample-rate-hz = <200000>;
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atmel,max-sample-rate-hz = <20000000>;
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atmel,startup-time-ms = <4>;
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vddana-supply = <&vdd_3v3_lp_reg>;
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vref-supply = <&vdd_3v3_lp_reg>;
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atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
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dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
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dma-names = "rx";
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}
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