mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 04:26:42 +07:00
cf0d19fb30
add simple-bus compatible property to soc nodes for 83xx/85xx platforms
that were missing them. Add same to platform probe code.
This fixes SoC device drivers (such as talitos) to succeed in matching
devices present in the soc node.
also update mpc836x_rdk dts to new SEC bindings (overlooked in commit
3fd4473: powerpc/fsl: update crypto node definition and device tree
instances).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
506 lines
12 KiB
Plaintext
506 lines
12 KiB
Plaintext
/*
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* MPC8568E MDS Device Tree Source
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*
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* Copyright 2007, 2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "MPC8568EMDS";
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compatible = "MPC8568EMDS", "MPC85xxMDS";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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ethernet2 = &enet2;
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ethernet3 = &enet3;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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pci1 = &pci1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8568@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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bcsr@f8000000 {
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device_type = "board-control";
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reg = <0xf8000000 0x8000>;
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};
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soc8568@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x100000>;
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reg = <0xe0000000 0x1000>;
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bus-frequency = <0>;
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memory-controller@2000 {
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compatible = "fsl,8568-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,8568-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>; // 32 bytes
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cache-size = <0x80000>; // L2, 512K
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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rtc@68 {
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compatible = "dallas,ds1374";
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reg = <0x68>;
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};
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8568-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8568-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8568-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8568-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x24520 0x20>;
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phy0: ethernet-phy@7 {
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interrupt-parent = <&mpic>;
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interrupts = <1 1>;
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reg = <0x7>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1>;
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reg = <0x1>;
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device_type = "ethernet-phy";
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <1 1>;
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reg = <0x2>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1>;
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reg = <0x3>;
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device_type = "ethernet-phy";
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};
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};
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enet0: ethernet@24000 {
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy2>;
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};
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enet1: ethernet@25000 {
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 2 36 2 40 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy3>;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { //global utilities block
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compatible = "fsl,mpc8548-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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crypto@30000 {
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compatible = "fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <45 2>;
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interrupt-parent = <&mpic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0xfe>;
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fsl,descriptor-types-mask = <0x12b0ebf>;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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par_io@e0100 {
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reg = <0xe0100 0x100>;
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device_type = "par_io";
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num-ports = <7>;
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pio1: ucc_pin@01 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
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0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
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0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
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0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
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0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
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0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
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0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
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0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
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0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
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0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
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0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
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0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
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0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
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0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
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0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
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0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
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0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
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0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
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0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
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0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
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0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
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0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
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0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
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};
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pio2: ucc_pin@02 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
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0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
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0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
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0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
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0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
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0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
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0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
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0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
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0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
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0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
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0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
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0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
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0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
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0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
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0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
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0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
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0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
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0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
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0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
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0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
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0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
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0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
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0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
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0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
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0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
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};
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};
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};
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qe@e0080000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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ranges = <0x0 0xe0080000 0x40000>;
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reg = <0xe0080000 0x480>;
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brg-frequency = <0>;
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bus-frequency = <396000000>;
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muram@10000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0x0 0x10000 0x10000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0x0 0x10000>;
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};
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};
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spi@4c0 {
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cell-index = <0>;
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compatible = "fsl,spi";
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reg = <0x4c0 0x40>;
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interrupts = <2>;
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interrupt-parent = <&qeic>;
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mode = "cpu";
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};
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spi@500 {
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cell-index = <1>;
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compatible = "fsl,spi";
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reg = <0x500 0x40>;
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interrupts = <1>;
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interrupt-parent = <&qeic>;
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mode = "cpu";
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};
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enet2: ucc@2000 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <1>;
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reg = <0x2000 0x200>;
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interrupts = <32>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk16";
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pio-handle = <&pio1>;
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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enet3: ucc@3000 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <2>;
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reg = <0x3000 0x200>;
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interrupts = <33>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk16";
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pio-handle = <&pio2>;
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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mdio@2120 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2120 0x18>;
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compatible = "fsl,ucc-mdio";
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/* These are the same PHYs as on
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* gianfar's MDIO bus */
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qe_phy0: ethernet-phy@07 {
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interrupt-parent = <&mpic>;
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interrupts = <1 1>;
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reg = <0x7>;
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device_type = "ethernet-phy";
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};
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qe_phy1: ethernet-phy@01 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1>;
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reg = <0x1>;
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device_type = "ethernet-phy";
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};
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qe_phy2: ethernet-phy@02 {
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interrupt-parent = <&mpic>;
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interrupts = <1 1>;
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reg = <0x2>;
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device_type = "ethernet-phy";
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};
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qe_phy3: ethernet-phy@03 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1>;
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reg = <0x3>;
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device_type = "ethernet-phy";
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};
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};
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qeic: interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x80 0x80>;
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big-endian;
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interrupts = <46 2 46 2>; //high:30 low:30
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interrupt-parent = <&mpic>;
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};
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};
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pci0: pci@e0008000 {
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cell-index = <0>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x12 AD18 */
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0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
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0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
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0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
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0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
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/* IDSEL 0x13 AD19 */
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0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
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0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
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0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
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0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
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interrupt-parent = <&mpic>;
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interrupts = <24 2>;
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bus-range = <0 255>;
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ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
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clock-frequency = <66666666>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008000 0x1000>;
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compatible = "fsl,mpc8540-pci";
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device_type = "pci";
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};
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/* PCI Express */
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pci1: pcie@e000a000 {
|
|
cell-index = <2>;
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
interrupt-map = <
|
|
|
|
/* IDSEL 0x0 (PEX) */
|
|
00000 0x0 0x0 0x1 &mpic 0x0 0x1
|
|
00000 0x0 0x0 0x2 &mpic 0x1 0x1
|
|
00000 0x0 0x0 0x3 &mpic 0x2 0x1
|
|
00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
|
|
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <26 2>;
|
|
bus-range = <0 255>;
|
|
ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
|
|
0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
|
|
clock-frequency = <33333333>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
reg = <0xe000a000 0x1000>;
|
|
compatible = "fsl,mpc8548-pcie";
|
|
device_type = "pci";
|
|
pcie@0 {
|
|
reg = <0x0 0x0 0x0 0x0 0x0>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
ranges = <0x2000000 0x0 0xa0000000
|
|
0x2000000 0x0 0xa0000000
|
|
0x0 0x10000000
|
|
|
|
0x1000000 0x0 0x0
|
|
0x1000000 0x0 0x0
|
|
0x0 0x800000>;
|
|
};
|
|
};
|
|
};
|