mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 19:41:34 +07:00
b113da6578
The transparent huge page code passes a PMD pointer in as the third argument of update_mmu_cache(), which expects a PTE pointer. This never got noticed because X86 implements update_mmu_cache() as a macro and thus we don't get any type checking, and X86 is the only architecture which supports transparent huge pages currently. Before other architectures can support transparent huge pages properly we need to add a new interface which will take a PMD pointer as the third argument rather than a PTE pointer. [akpm@linux-foundation.org: implement update_mm_cache_pmd() for s390] Signed-off-by: David S. Miller <davem@davemloft.net> Cc: Andrea Arcangeli <aarcange@redhat.com> Cc: Johannes Weiner <hannes@cmpxchg.org> Cc: Gerald Schaefer <gerald.schaefer@de.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
189 lines
4.8 KiB
C
189 lines
4.8 KiB
C
#ifndef _ASM_X86_PGTABLE_64_H
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#define _ASM_X86_PGTABLE_64_H
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#include <linux/const.h>
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#include <asm/pgtable_64_types.h>
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#ifndef __ASSEMBLY__
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/*
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* This file contains the functions and defines necessary to modify and use
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* the x86-64 page table tree.
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*/
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#include <asm/processor.h>
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#include <linux/bitops.h>
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#include <linux/threads.h>
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extern pud_t level3_kernel_pgt[512];
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extern pud_t level3_ident_pgt[512];
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extern pmd_t level2_kernel_pgt[512];
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extern pmd_t level2_fixmap_pgt[512];
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extern pmd_t level2_ident_pgt[512];
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extern pgd_t init_level4_pgt[];
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#define swapper_pg_dir init_level4_pgt
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extern void paging_init(void);
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#define pte_ERROR(e) \
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pr_err("%s:%d: bad pte %p(%016lx)\n", \
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__FILE__, __LINE__, &(e), pte_val(e))
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#define pmd_ERROR(e) \
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pr_err("%s:%d: bad pmd %p(%016lx)\n", \
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__FILE__, __LINE__, &(e), pmd_val(e))
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#define pud_ERROR(e) \
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pr_err("%s:%d: bad pud %p(%016lx)\n", \
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__FILE__, __LINE__, &(e), pud_val(e))
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#define pgd_ERROR(e) \
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pr_err("%s:%d: bad pgd %p(%016lx)\n", \
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__FILE__, __LINE__, &(e), pgd_val(e))
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struct mm_struct;
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void set_pte_vaddr_pud(pud_t *pud_page, unsigned long vaddr, pte_t new_pte);
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static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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*ptep = native_make_pte(0);
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}
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static inline void native_set_pte(pte_t *ptep, pte_t pte)
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{
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*ptep = pte;
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}
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static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
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{
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native_set_pte(ptep, pte);
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}
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static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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*pmdp = pmd;
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}
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static inline void native_pmd_clear(pmd_t *pmd)
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{
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native_set_pmd(pmd, native_make_pmd(0));
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}
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static inline pte_t native_ptep_get_and_clear(pte_t *xp)
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{
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#ifdef CONFIG_SMP
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return native_make_pte(xchg(&xp->pte, 0));
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#else
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/* native_local_ptep_get_and_clear,
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but duplicated because of cyclic dependency */
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pte_t ret = *xp;
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native_pte_clear(NULL, 0, xp);
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return ret;
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#endif
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}
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static inline pmd_t native_pmdp_get_and_clear(pmd_t *xp)
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{
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#ifdef CONFIG_SMP
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return native_make_pmd(xchg(&xp->pmd, 0));
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#else
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/* native_local_pmdp_get_and_clear,
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but duplicated because of cyclic dependency */
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pmd_t ret = *xp;
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native_pmd_clear(xp);
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return ret;
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#endif
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}
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static inline void native_set_pud(pud_t *pudp, pud_t pud)
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{
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*pudp = pud;
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}
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static inline void native_pud_clear(pud_t *pud)
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{
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native_set_pud(pud, native_make_pud(0));
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}
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static inline void native_set_pgd(pgd_t *pgdp, pgd_t pgd)
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{
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*pgdp = pgd;
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}
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static inline void native_pgd_clear(pgd_t *pgd)
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{
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native_set_pgd(pgd, native_make_pgd(0));
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}
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extern void sync_global_pgds(unsigned long start, unsigned long end);
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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/*
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* Level 4 access.
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*/
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static inline int pgd_large(pgd_t pgd) { return 0; }
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#define mk_kernel_pgd(address) __pgd((address) | _KERNPG_TABLE)
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/* PUD - Level3 access */
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/* PMD - Level 2 access */
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#define pte_to_pgoff(pte) ((pte_val((pte)) & PHYSICAL_PAGE_MASK) >> PAGE_SHIFT)
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#define pgoff_to_pte(off) ((pte_t) { .pte = ((off) << PAGE_SHIFT) | \
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_PAGE_FILE })
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#define PTE_FILE_MAX_BITS __PHYSICAL_MASK_SHIFT
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/* PTE - Level 1 access. */
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/* x86-64 always has all page tables mapped. */
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#define pte_offset_map(dir, address) pte_offset_kernel((dir), (address))
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#define pte_unmap(pte) ((void)(pte))/* NOP */
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#define update_mmu_cache(vma, address, ptep) do { } while (0)
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#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
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/* Encode and de-code a swap entry */
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#if _PAGE_BIT_FILE < _PAGE_BIT_PROTNONE
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#define SWP_TYPE_BITS (_PAGE_BIT_FILE - _PAGE_BIT_PRESENT - 1)
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#define SWP_OFFSET_SHIFT (_PAGE_BIT_PROTNONE + 1)
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#else
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#define SWP_TYPE_BITS (_PAGE_BIT_PROTNONE - _PAGE_BIT_PRESENT - 1)
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#define SWP_OFFSET_SHIFT (_PAGE_BIT_FILE + 1)
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#endif
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#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
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#define __swp_type(x) (((x).val >> (_PAGE_BIT_PRESENT + 1)) \
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& ((1U << SWP_TYPE_BITS) - 1))
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#define __swp_offset(x) ((x).val >> SWP_OFFSET_SHIFT)
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#define __swp_entry(type, offset) ((swp_entry_t) { \
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((type) << (_PAGE_BIT_PRESENT + 1)) \
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| ((offset) << SWP_OFFSET_SHIFT) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) })
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#define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val })
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extern int kern_addr_valid(unsigned long addr);
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extern void cleanup_highmap(void);
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#define HAVE_ARCH_UNMAPPED_AREA
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#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
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#define pgtable_cache_init() do { } while (0)
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#define check_pgt_cache() do { } while (0)
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#define PAGE_AGP PAGE_KERNEL_NOCACHE
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#define HAVE_PAGE_AGP 1
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/* fs/proc/kcore.c */
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#define kc_vaddr_to_offset(v) ((v) & __VIRTUAL_MASK)
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#define kc_offset_to_vaddr(o) ((o) | ~__VIRTUAL_MASK)
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#define __HAVE_ARCH_PTE_SAME
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_X86_PGTABLE_64_H */
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