mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
2030abddec
If RoCE PDUs being sent or received contain pad bytes, then the iCRC
is miscalculated, resulting in PDUs being emitted by RXE with an incorrect
iCRC, as well as ingress PDUs being dropped due to erroneously detecting
a bad iCRC in the PDU. The fix is to include the pad bytes, if any,
in iCRC computations.
Note: This bug has caused broken on-the-wire compatibility with actual
hardware RoCE devices since the soft-RoCE driver was first put into the
mainstream kernel. Fixing it will create an incompatibility with the
original soft-RoCE devices, but is necessary to be compatible with real
hardware devices.
Fixes: 8700e3e7c4
("Soft RoCE driver")
Signed-off-by: Steve Wise <larrystevenwise@gmail.com>
Link: https://lore.kernel.org/r/20191203020319.15036-2-larrystevenwise@gmail.com
Signed-off-by: Doug Ledford <dledford@redhat.com>
765 lines
19 KiB
C
765 lines
19 KiB
C
/*
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* Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.
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* Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/skbuff.h>
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#include <crypto/hash.h>
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#include "rxe.h"
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#include "rxe_loc.h"
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#include "rxe_queue.h"
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static int next_opcode(struct rxe_qp *qp, struct rxe_send_wqe *wqe,
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u32 opcode);
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static inline void retry_first_write_send(struct rxe_qp *qp,
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struct rxe_send_wqe *wqe,
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unsigned int mask, int npsn)
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{
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int i;
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for (i = 0; i < npsn; i++) {
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int to_send = (wqe->dma.resid > qp->mtu) ?
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qp->mtu : wqe->dma.resid;
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qp->req.opcode = next_opcode(qp, wqe,
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wqe->wr.opcode);
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if (wqe->wr.send_flags & IB_SEND_INLINE) {
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wqe->dma.resid -= to_send;
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wqe->dma.sge_offset += to_send;
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} else {
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advance_dma_data(&wqe->dma, to_send);
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}
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if (mask & WR_WRITE_MASK)
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wqe->iova += qp->mtu;
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}
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}
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static void req_retry(struct rxe_qp *qp)
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{
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struct rxe_send_wqe *wqe;
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unsigned int wqe_index;
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unsigned int mask;
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int npsn;
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int first = 1;
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qp->req.wqe_index = consumer_index(qp->sq.queue);
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qp->req.psn = qp->comp.psn;
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qp->req.opcode = -1;
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for (wqe_index = consumer_index(qp->sq.queue);
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wqe_index != producer_index(qp->sq.queue);
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wqe_index = next_index(qp->sq.queue, wqe_index)) {
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wqe = addr_from_index(qp->sq.queue, wqe_index);
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mask = wr_opcode_mask(wqe->wr.opcode, qp);
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if (wqe->state == wqe_state_posted)
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break;
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if (wqe->state == wqe_state_done)
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continue;
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wqe->iova = (mask & WR_ATOMIC_MASK) ?
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wqe->wr.wr.atomic.remote_addr :
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(mask & WR_READ_OR_WRITE_MASK) ?
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wqe->wr.wr.rdma.remote_addr :
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0;
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if (!first || (mask & WR_READ_MASK) == 0) {
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wqe->dma.resid = wqe->dma.length;
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wqe->dma.cur_sge = 0;
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wqe->dma.sge_offset = 0;
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}
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if (first) {
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first = 0;
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if (mask & WR_WRITE_OR_SEND_MASK) {
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npsn = (qp->comp.psn - wqe->first_psn) &
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BTH_PSN_MASK;
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retry_first_write_send(qp, wqe, mask, npsn);
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}
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if (mask & WR_READ_MASK) {
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npsn = (wqe->dma.length - wqe->dma.resid) /
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qp->mtu;
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wqe->iova += npsn * qp->mtu;
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}
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}
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wqe->state = wqe_state_posted;
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}
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}
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void rnr_nak_timer(struct timer_list *t)
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{
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struct rxe_qp *qp = from_timer(qp, t, rnr_nak_timer);
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pr_debug("qp#%d rnr nak timer fired\n", qp_num(qp));
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rxe_run_task(&qp->req.task, 1);
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}
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static struct rxe_send_wqe *req_next_wqe(struct rxe_qp *qp)
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{
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struct rxe_send_wqe *wqe = queue_head(qp->sq.queue);
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unsigned long flags;
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if (unlikely(qp->req.state == QP_STATE_DRAIN)) {
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/* check to see if we are drained;
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* state_lock used by requester and completer
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*/
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spin_lock_irqsave(&qp->state_lock, flags);
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do {
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if (qp->req.state != QP_STATE_DRAIN) {
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/* comp just finished */
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spin_unlock_irqrestore(&qp->state_lock,
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flags);
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break;
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}
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if (wqe && ((qp->req.wqe_index !=
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consumer_index(qp->sq.queue)) ||
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(wqe->state != wqe_state_posted))) {
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/* comp not done yet */
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spin_unlock_irqrestore(&qp->state_lock,
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flags);
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break;
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}
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qp->req.state = QP_STATE_DRAINED;
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spin_unlock_irqrestore(&qp->state_lock, flags);
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if (qp->ibqp.event_handler) {
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struct ib_event ev;
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ev.device = qp->ibqp.device;
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ev.element.qp = &qp->ibqp;
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ev.event = IB_EVENT_SQ_DRAINED;
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qp->ibqp.event_handler(&ev,
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qp->ibqp.qp_context);
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}
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} while (0);
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}
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if (qp->req.wqe_index == producer_index(qp->sq.queue))
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return NULL;
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wqe = addr_from_index(qp->sq.queue, qp->req.wqe_index);
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if (unlikely((qp->req.state == QP_STATE_DRAIN ||
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qp->req.state == QP_STATE_DRAINED) &&
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(wqe->state != wqe_state_processing)))
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return NULL;
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if (unlikely((wqe->wr.send_flags & IB_SEND_FENCE) &&
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(qp->req.wqe_index != consumer_index(qp->sq.queue)))) {
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qp->req.wait_fence = 1;
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return NULL;
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}
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wqe->mask = wr_opcode_mask(wqe->wr.opcode, qp);
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return wqe;
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}
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static int next_opcode_rc(struct rxe_qp *qp, u32 opcode, int fits)
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{
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switch (opcode) {
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case IB_WR_RDMA_WRITE:
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if (qp->req.opcode == IB_OPCODE_RC_RDMA_WRITE_FIRST ||
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qp->req.opcode == IB_OPCODE_RC_RDMA_WRITE_MIDDLE)
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return fits ?
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IB_OPCODE_RC_RDMA_WRITE_LAST :
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IB_OPCODE_RC_RDMA_WRITE_MIDDLE;
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else
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return fits ?
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IB_OPCODE_RC_RDMA_WRITE_ONLY :
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IB_OPCODE_RC_RDMA_WRITE_FIRST;
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case IB_WR_RDMA_WRITE_WITH_IMM:
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if (qp->req.opcode == IB_OPCODE_RC_RDMA_WRITE_FIRST ||
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qp->req.opcode == IB_OPCODE_RC_RDMA_WRITE_MIDDLE)
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return fits ?
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IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE :
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IB_OPCODE_RC_RDMA_WRITE_MIDDLE;
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else
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return fits ?
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IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE :
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IB_OPCODE_RC_RDMA_WRITE_FIRST;
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case IB_WR_SEND:
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if (qp->req.opcode == IB_OPCODE_RC_SEND_FIRST ||
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qp->req.opcode == IB_OPCODE_RC_SEND_MIDDLE)
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return fits ?
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IB_OPCODE_RC_SEND_LAST :
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IB_OPCODE_RC_SEND_MIDDLE;
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else
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return fits ?
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IB_OPCODE_RC_SEND_ONLY :
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IB_OPCODE_RC_SEND_FIRST;
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case IB_WR_SEND_WITH_IMM:
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if (qp->req.opcode == IB_OPCODE_RC_SEND_FIRST ||
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qp->req.opcode == IB_OPCODE_RC_SEND_MIDDLE)
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return fits ?
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IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE :
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IB_OPCODE_RC_SEND_MIDDLE;
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else
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return fits ?
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IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE :
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IB_OPCODE_RC_SEND_FIRST;
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case IB_WR_RDMA_READ:
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return IB_OPCODE_RC_RDMA_READ_REQUEST;
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case IB_WR_ATOMIC_CMP_AND_SWP:
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return IB_OPCODE_RC_COMPARE_SWAP;
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case IB_WR_ATOMIC_FETCH_AND_ADD:
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return IB_OPCODE_RC_FETCH_ADD;
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case IB_WR_SEND_WITH_INV:
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if (qp->req.opcode == IB_OPCODE_RC_SEND_FIRST ||
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qp->req.opcode == IB_OPCODE_RC_SEND_MIDDLE)
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return fits ? IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE :
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IB_OPCODE_RC_SEND_MIDDLE;
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else
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return fits ? IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE :
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IB_OPCODE_RC_SEND_FIRST;
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case IB_WR_REG_MR:
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case IB_WR_LOCAL_INV:
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return opcode;
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}
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return -EINVAL;
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}
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static int next_opcode_uc(struct rxe_qp *qp, u32 opcode, int fits)
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{
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switch (opcode) {
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case IB_WR_RDMA_WRITE:
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if (qp->req.opcode == IB_OPCODE_UC_RDMA_WRITE_FIRST ||
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qp->req.opcode == IB_OPCODE_UC_RDMA_WRITE_MIDDLE)
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return fits ?
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IB_OPCODE_UC_RDMA_WRITE_LAST :
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IB_OPCODE_UC_RDMA_WRITE_MIDDLE;
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else
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return fits ?
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IB_OPCODE_UC_RDMA_WRITE_ONLY :
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IB_OPCODE_UC_RDMA_WRITE_FIRST;
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case IB_WR_RDMA_WRITE_WITH_IMM:
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if (qp->req.opcode == IB_OPCODE_UC_RDMA_WRITE_FIRST ||
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qp->req.opcode == IB_OPCODE_UC_RDMA_WRITE_MIDDLE)
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return fits ?
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IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE :
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IB_OPCODE_UC_RDMA_WRITE_MIDDLE;
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else
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return fits ?
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IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE :
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IB_OPCODE_UC_RDMA_WRITE_FIRST;
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case IB_WR_SEND:
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if (qp->req.opcode == IB_OPCODE_UC_SEND_FIRST ||
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qp->req.opcode == IB_OPCODE_UC_SEND_MIDDLE)
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return fits ?
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IB_OPCODE_UC_SEND_LAST :
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IB_OPCODE_UC_SEND_MIDDLE;
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else
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return fits ?
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IB_OPCODE_UC_SEND_ONLY :
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IB_OPCODE_UC_SEND_FIRST;
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case IB_WR_SEND_WITH_IMM:
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if (qp->req.opcode == IB_OPCODE_UC_SEND_FIRST ||
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qp->req.opcode == IB_OPCODE_UC_SEND_MIDDLE)
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return fits ?
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IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE :
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IB_OPCODE_UC_SEND_MIDDLE;
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else
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return fits ?
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IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE :
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IB_OPCODE_UC_SEND_FIRST;
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}
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return -EINVAL;
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}
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static int next_opcode(struct rxe_qp *qp, struct rxe_send_wqe *wqe,
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u32 opcode)
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{
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int fits = (wqe->dma.resid <= qp->mtu);
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switch (qp_type(qp)) {
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case IB_QPT_RC:
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return next_opcode_rc(qp, opcode, fits);
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case IB_QPT_UC:
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return next_opcode_uc(qp, opcode, fits);
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case IB_QPT_SMI:
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case IB_QPT_UD:
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case IB_QPT_GSI:
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switch (opcode) {
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case IB_WR_SEND:
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return IB_OPCODE_UD_SEND_ONLY;
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case IB_WR_SEND_WITH_IMM:
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return IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
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}
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break;
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default:
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break;
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}
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return -EINVAL;
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}
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static inline int check_init_depth(struct rxe_qp *qp, struct rxe_send_wqe *wqe)
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{
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int depth;
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if (wqe->has_rd_atomic)
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return 0;
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qp->req.need_rd_atomic = 1;
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depth = atomic_dec_return(&qp->req.rd_atomic);
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if (depth >= 0) {
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qp->req.need_rd_atomic = 0;
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wqe->has_rd_atomic = 1;
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return 0;
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}
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atomic_inc(&qp->req.rd_atomic);
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return -EAGAIN;
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}
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static inline int get_mtu(struct rxe_qp *qp)
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{
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struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
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if ((qp_type(qp) == IB_QPT_RC) || (qp_type(qp) == IB_QPT_UC))
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return qp->mtu;
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return rxe->port.mtu_cap;
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}
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static struct sk_buff *init_req_packet(struct rxe_qp *qp,
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struct rxe_send_wqe *wqe,
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int opcode, int payload,
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struct rxe_pkt_info *pkt)
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{
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struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
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struct rxe_port *port = &rxe->port;
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struct sk_buff *skb;
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struct rxe_send_wr *ibwr = &wqe->wr;
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struct rxe_av *av;
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int pad = (-payload) & 0x3;
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int paylen;
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int solicited;
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u16 pkey;
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u32 qp_num;
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int ack_req;
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/* length from start of bth to end of icrc */
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paylen = rxe_opcode[opcode].length + payload + pad + RXE_ICRC_SIZE;
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/* pkt->hdr, rxe, port_num and mask are initialized in ifc
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* layer
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*/
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pkt->opcode = opcode;
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pkt->qp = qp;
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pkt->psn = qp->req.psn;
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pkt->mask = rxe_opcode[opcode].mask;
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pkt->paylen = paylen;
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pkt->offset = 0;
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pkt->wqe = wqe;
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/* init skb */
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av = rxe_get_av(pkt);
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skb = rxe_init_packet(rxe, av, paylen, pkt);
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if (unlikely(!skb))
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return NULL;
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/* init bth */
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solicited = (ibwr->send_flags & IB_SEND_SOLICITED) &&
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(pkt->mask & RXE_END_MASK) &&
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((pkt->mask & (RXE_SEND_MASK)) ||
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(pkt->mask & (RXE_WRITE_MASK | RXE_IMMDT_MASK)) ==
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(RXE_WRITE_MASK | RXE_IMMDT_MASK));
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pkey = (qp_type(qp) == IB_QPT_GSI) ?
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port->pkey_tbl[ibwr->wr.ud.pkey_index] :
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port->pkey_tbl[qp->attr.pkey_index];
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qp_num = (pkt->mask & RXE_DETH_MASK) ? ibwr->wr.ud.remote_qpn :
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qp->attr.dest_qp_num;
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ack_req = ((pkt->mask & RXE_END_MASK) ||
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(qp->req.noack_pkts++ > RXE_MAX_PKT_PER_ACK));
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if (ack_req)
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qp->req.noack_pkts = 0;
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bth_init(pkt, pkt->opcode, solicited, 0, pad, pkey, qp_num,
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ack_req, pkt->psn);
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/* init optional headers */
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if (pkt->mask & RXE_RETH_MASK) {
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reth_set_rkey(pkt, ibwr->wr.rdma.rkey);
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reth_set_va(pkt, wqe->iova);
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reth_set_len(pkt, wqe->dma.resid);
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}
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if (pkt->mask & RXE_IMMDT_MASK)
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immdt_set_imm(pkt, ibwr->ex.imm_data);
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if (pkt->mask & RXE_IETH_MASK)
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ieth_set_rkey(pkt, ibwr->ex.invalidate_rkey);
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if (pkt->mask & RXE_ATMETH_MASK) {
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atmeth_set_va(pkt, wqe->iova);
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if (opcode == IB_OPCODE_RC_COMPARE_SWAP ||
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opcode == IB_OPCODE_RD_COMPARE_SWAP) {
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atmeth_set_swap_add(pkt, ibwr->wr.atomic.swap);
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atmeth_set_comp(pkt, ibwr->wr.atomic.compare_add);
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|
} else {
|
|
atmeth_set_swap_add(pkt, ibwr->wr.atomic.compare_add);
|
|
}
|
|
atmeth_set_rkey(pkt, ibwr->wr.atomic.rkey);
|
|
}
|
|
|
|
if (pkt->mask & RXE_DETH_MASK) {
|
|
if (qp->ibqp.qp_num == 1)
|
|
deth_set_qkey(pkt, GSI_QKEY);
|
|
else
|
|
deth_set_qkey(pkt, ibwr->wr.ud.remote_qkey);
|
|
deth_set_sqp(pkt, qp->ibqp.qp_num);
|
|
}
|
|
|
|
return skb;
|
|
}
|
|
|
|
static int fill_packet(struct rxe_qp *qp, struct rxe_send_wqe *wqe,
|
|
struct rxe_pkt_info *pkt, struct sk_buff *skb,
|
|
int paylen)
|
|
{
|
|
struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
|
|
u32 crc = 0;
|
|
u32 *p;
|
|
int err;
|
|
|
|
err = rxe_prepare(pkt, skb, &crc);
|
|
if (err)
|
|
return err;
|
|
|
|
if (pkt->mask & RXE_WRITE_OR_SEND) {
|
|
if (wqe->wr.send_flags & IB_SEND_INLINE) {
|
|
u8 *tmp = &wqe->dma.inline_data[wqe->dma.sge_offset];
|
|
|
|
crc = rxe_crc32(rxe, crc, tmp, paylen);
|
|
memcpy(payload_addr(pkt), tmp, paylen);
|
|
|
|
wqe->dma.resid -= paylen;
|
|
wqe->dma.sge_offset += paylen;
|
|
} else {
|
|
err = copy_data(qp->pd, 0, &wqe->dma,
|
|
payload_addr(pkt), paylen,
|
|
from_mem_obj,
|
|
&crc);
|
|
if (err)
|
|
return err;
|
|
}
|
|
if (bth_pad(pkt)) {
|
|
u8 *pad = payload_addr(pkt) + paylen;
|
|
|
|
memset(pad, 0, bth_pad(pkt));
|
|
crc = rxe_crc32(rxe, crc, pad, bth_pad(pkt));
|
|
}
|
|
}
|
|
p = payload_addr(pkt) + paylen + bth_pad(pkt);
|
|
|
|
*p = ~crc;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void update_wqe_state(struct rxe_qp *qp,
|
|
struct rxe_send_wqe *wqe,
|
|
struct rxe_pkt_info *pkt)
|
|
{
|
|
if (pkt->mask & RXE_END_MASK) {
|
|
if (qp_type(qp) == IB_QPT_RC)
|
|
wqe->state = wqe_state_pending;
|
|
} else {
|
|
wqe->state = wqe_state_processing;
|
|
}
|
|
}
|
|
|
|
static void update_wqe_psn(struct rxe_qp *qp,
|
|
struct rxe_send_wqe *wqe,
|
|
struct rxe_pkt_info *pkt,
|
|
int payload)
|
|
{
|
|
/* number of packets left to send including current one */
|
|
int num_pkt = (wqe->dma.resid + payload + qp->mtu - 1) / qp->mtu;
|
|
|
|
/* handle zero length packet case */
|
|
if (num_pkt == 0)
|
|
num_pkt = 1;
|
|
|
|
if (pkt->mask & RXE_START_MASK) {
|
|
wqe->first_psn = qp->req.psn;
|
|
wqe->last_psn = (qp->req.psn + num_pkt - 1) & BTH_PSN_MASK;
|
|
}
|
|
|
|
if (pkt->mask & RXE_READ_MASK)
|
|
qp->req.psn = (wqe->first_psn + num_pkt) & BTH_PSN_MASK;
|
|
else
|
|
qp->req.psn = (qp->req.psn + 1) & BTH_PSN_MASK;
|
|
}
|
|
|
|
static void save_state(struct rxe_send_wqe *wqe,
|
|
struct rxe_qp *qp,
|
|
struct rxe_send_wqe *rollback_wqe,
|
|
u32 *rollback_psn)
|
|
{
|
|
rollback_wqe->state = wqe->state;
|
|
rollback_wqe->first_psn = wqe->first_psn;
|
|
rollback_wqe->last_psn = wqe->last_psn;
|
|
*rollback_psn = qp->req.psn;
|
|
}
|
|
|
|
static void rollback_state(struct rxe_send_wqe *wqe,
|
|
struct rxe_qp *qp,
|
|
struct rxe_send_wqe *rollback_wqe,
|
|
u32 rollback_psn)
|
|
{
|
|
wqe->state = rollback_wqe->state;
|
|
wqe->first_psn = rollback_wqe->first_psn;
|
|
wqe->last_psn = rollback_wqe->last_psn;
|
|
qp->req.psn = rollback_psn;
|
|
}
|
|
|
|
static void update_state(struct rxe_qp *qp, struct rxe_send_wqe *wqe,
|
|
struct rxe_pkt_info *pkt, int payload)
|
|
{
|
|
qp->req.opcode = pkt->opcode;
|
|
|
|
if (pkt->mask & RXE_END_MASK)
|
|
qp->req.wqe_index = next_index(qp->sq.queue, qp->req.wqe_index);
|
|
|
|
qp->need_req_skb = 0;
|
|
|
|
if (qp->qp_timeout_jiffies && !timer_pending(&qp->retrans_timer))
|
|
mod_timer(&qp->retrans_timer,
|
|
jiffies + qp->qp_timeout_jiffies);
|
|
}
|
|
|
|
int rxe_requester(void *arg)
|
|
{
|
|
struct rxe_qp *qp = (struct rxe_qp *)arg;
|
|
struct rxe_pkt_info pkt;
|
|
struct sk_buff *skb;
|
|
struct rxe_send_wqe *wqe;
|
|
enum rxe_hdr_mask mask;
|
|
int payload;
|
|
int mtu;
|
|
int opcode;
|
|
int ret;
|
|
struct rxe_send_wqe rollback_wqe;
|
|
u32 rollback_psn;
|
|
|
|
rxe_add_ref(qp);
|
|
|
|
next_wqe:
|
|
if (unlikely(!qp->valid || qp->req.state == QP_STATE_ERROR))
|
|
goto exit;
|
|
|
|
if (unlikely(qp->req.state == QP_STATE_RESET)) {
|
|
qp->req.wqe_index = consumer_index(qp->sq.queue);
|
|
qp->req.opcode = -1;
|
|
qp->req.need_rd_atomic = 0;
|
|
qp->req.wait_psn = 0;
|
|
qp->req.need_retry = 0;
|
|
goto exit;
|
|
}
|
|
|
|
if (unlikely(qp->req.need_retry)) {
|
|
req_retry(qp);
|
|
qp->req.need_retry = 0;
|
|
}
|
|
|
|
wqe = req_next_wqe(qp);
|
|
if (unlikely(!wqe))
|
|
goto exit;
|
|
|
|
if (wqe->mask & WR_REG_MASK) {
|
|
if (wqe->wr.opcode == IB_WR_LOCAL_INV) {
|
|
struct rxe_dev *rxe = to_rdev(qp->ibqp.device);
|
|
struct rxe_mem *rmr;
|
|
|
|
rmr = rxe_pool_get_index(&rxe->mr_pool,
|
|
wqe->wr.ex.invalidate_rkey >> 8);
|
|
if (!rmr) {
|
|
pr_err("No mr for key %#x\n",
|
|
wqe->wr.ex.invalidate_rkey);
|
|
wqe->state = wqe_state_error;
|
|
wqe->status = IB_WC_MW_BIND_ERR;
|
|
goto exit;
|
|
}
|
|
rmr->state = RXE_MEM_STATE_FREE;
|
|
rxe_drop_ref(rmr);
|
|
wqe->state = wqe_state_done;
|
|
wqe->status = IB_WC_SUCCESS;
|
|
} else if (wqe->wr.opcode == IB_WR_REG_MR) {
|
|
struct rxe_mem *rmr = to_rmr(wqe->wr.wr.reg.mr);
|
|
|
|
rmr->state = RXE_MEM_STATE_VALID;
|
|
rmr->access = wqe->wr.wr.reg.access;
|
|
rmr->lkey = wqe->wr.wr.reg.key;
|
|
rmr->rkey = wqe->wr.wr.reg.key;
|
|
rmr->iova = wqe->wr.wr.reg.mr->iova;
|
|
wqe->state = wqe_state_done;
|
|
wqe->status = IB_WC_SUCCESS;
|
|
} else {
|
|
goto exit;
|
|
}
|
|
if ((wqe->wr.send_flags & IB_SEND_SIGNALED) ||
|
|
qp->sq_sig_type == IB_SIGNAL_ALL_WR)
|
|
rxe_run_task(&qp->comp.task, 1);
|
|
qp->req.wqe_index = next_index(qp->sq.queue,
|
|
qp->req.wqe_index);
|
|
goto next_wqe;
|
|
}
|
|
|
|
if (unlikely(qp_type(qp) == IB_QPT_RC &&
|
|
qp->req.psn > (qp->comp.psn + RXE_MAX_UNACKED_PSNS))) {
|
|
qp->req.wait_psn = 1;
|
|
goto exit;
|
|
}
|
|
|
|
/* Limit the number of inflight SKBs per QP */
|
|
if (unlikely(atomic_read(&qp->skb_out) >
|
|
RXE_INFLIGHT_SKBS_PER_QP_HIGH)) {
|
|
qp->need_req_skb = 1;
|
|
goto exit;
|
|
}
|
|
|
|
opcode = next_opcode(qp, wqe, wqe->wr.opcode);
|
|
if (unlikely(opcode < 0)) {
|
|
wqe->status = IB_WC_LOC_QP_OP_ERR;
|
|
goto exit;
|
|
}
|
|
|
|
mask = rxe_opcode[opcode].mask;
|
|
if (unlikely(mask & RXE_READ_OR_ATOMIC)) {
|
|
if (check_init_depth(qp, wqe))
|
|
goto exit;
|
|
}
|
|
|
|
mtu = get_mtu(qp);
|
|
payload = (mask & RXE_WRITE_OR_SEND) ? wqe->dma.resid : 0;
|
|
if (payload > mtu) {
|
|
if (qp_type(qp) == IB_QPT_UD) {
|
|
/* C10-93.1.1: If the total sum of all the buffer lengths specified for a
|
|
* UD message exceeds the MTU of the port as returned by QueryHCA, the CI
|
|
* shall not emit any packets for this message. Further, the CI shall not
|
|
* generate an error due to this condition.
|
|
*/
|
|
|
|
/* fake a successful UD send */
|
|
wqe->first_psn = qp->req.psn;
|
|
wqe->last_psn = qp->req.psn;
|
|
qp->req.psn = (qp->req.psn + 1) & BTH_PSN_MASK;
|
|
qp->req.opcode = IB_OPCODE_UD_SEND_ONLY;
|
|
qp->req.wqe_index = next_index(qp->sq.queue,
|
|
qp->req.wqe_index);
|
|
wqe->state = wqe_state_done;
|
|
wqe->status = IB_WC_SUCCESS;
|
|
__rxe_do_task(&qp->comp.task);
|
|
rxe_drop_ref(qp);
|
|
return 0;
|
|
}
|
|
payload = mtu;
|
|
}
|
|
|
|
skb = init_req_packet(qp, wqe, opcode, payload, &pkt);
|
|
if (unlikely(!skb)) {
|
|
pr_err("qp#%d Failed allocating skb\n", qp_num(qp));
|
|
goto err;
|
|
}
|
|
|
|
if (fill_packet(qp, wqe, &pkt, skb, payload)) {
|
|
pr_debug("qp#%d Error during fill packet\n", qp_num(qp));
|
|
kfree_skb(skb);
|
|
goto err;
|
|
}
|
|
|
|
/*
|
|
* To prevent a race on wqe access between requester and completer,
|
|
* wqe members state and psn need to be set before calling
|
|
* rxe_xmit_packet().
|
|
* Otherwise, completer might initiate an unjustified retry flow.
|
|
*/
|
|
save_state(wqe, qp, &rollback_wqe, &rollback_psn);
|
|
update_wqe_state(qp, wqe, &pkt);
|
|
update_wqe_psn(qp, wqe, &pkt, payload);
|
|
ret = rxe_xmit_packet(qp, &pkt, skb);
|
|
if (ret) {
|
|
qp->need_req_skb = 1;
|
|
|
|
rollback_state(wqe, qp, &rollback_wqe, rollback_psn);
|
|
|
|
if (ret == -EAGAIN) {
|
|
rxe_run_task(&qp->req.task, 1);
|
|
goto exit;
|
|
}
|
|
|
|
goto err;
|
|
}
|
|
|
|
update_state(qp, wqe, &pkt, payload);
|
|
|
|
goto next_wqe;
|
|
|
|
err:
|
|
wqe->status = IB_WC_LOC_PROT_ERR;
|
|
wqe->state = wqe_state_error;
|
|
__rxe_do_task(&qp->comp.task);
|
|
|
|
exit:
|
|
rxe_drop_ref(qp);
|
|
return -EAGAIN;
|
|
}
|