mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 14:20:55 +07:00
956b9ba156
Use a more common debugging style. Remove __FILE__ uses, add missing newlines, coalesce formats and align arguments. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
236 lines
6.2 KiB
C
236 lines
6.2 KiB
C
#include "amd64_edac.h"
|
|
|
|
static ssize_t amd64_inject_section_show(struct device *dev,
|
|
struct device_attribute *mattr,
|
|
char *buf)
|
|
{
|
|
struct mem_ctl_info *mci = to_mci(dev);
|
|
struct amd64_pvt *pvt = mci->pvt_info;
|
|
return sprintf(buf, "0x%x\n", pvt->injection.section);
|
|
}
|
|
|
|
/*
|
|
* store error injection section value which refers to one of 4 16-byte sections
|
|
* within a 64-byte cacheline
|
|
*
|
|
* range: 0..3
|
|
*/
|
|
static ssize_t amd64_inject_section_store(struct device *dev,
|
|
struct device_attribute *mattr,
|
|
const char *data, size_t count)
|
|
{
|
|
struct mem_ctl_info *mci = to_mci(dev);
|
|
struct amd64_pvt *pvt = mci->pvt_info;
|
|
unsigned long value;
|
|
int ret = 0;
|
|
|
|
ret = strict_strtoul(data, 10, &value);
|
|
if (ret != -EINVAL) {
|
|
|
|
if (value > 3) {
|
|
amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
|
|
return -EINVAL;
|
|
}
|
|
|
|
pvt->injection.section = (u32) value;
|
|
return count;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static ssize_t amd64_inject_word_show(struct device *dev,
|
|
struct device_attribute *mattr,
|
|
char *buf)
|
|
{
|
|
struct mem_ctl_info *mci = to_mci(dev);
|
|
struct amd64_pvt *pvt = mci->pvt_info;
|
|
return sprintf(buf, "0x%x\n", pvt->injection.word);
|
|
}
|
|
|
|
/*
|
|
* store error injection word value which refers to one of 9 16-bit word of the
|
|
* 16-byte (128-bit + ECC bits) section
|
|
*
|
|
* range: 0..8
|
|
*/
|
|
static ssize_t amd64_inject_word_store(struct device *dev,
|
|
struct device_attribute *mattr,
|
|
const char *data, size_t count)
|
|
{
|
|
struct mem_ctl_info *mci = to_mci(dev);
|
|
struct amd64_pvt *pvt = mci->pvt_info;
|
|
unsigned long value;
|
|
int ret = 0;
|
|
|
|
ret = strict_strtoul(data, 10, &value);
|
|
if (ret != -EINVAL) {
|
|
|
|
if (value > 8) {
|
|
amd64_warn("%s: invalid word 0x%lx\n", __func__, value);
|
|
return -EINVAL;
|
|
}
|
|
|
|
pvt->injection.word = (u32) value;
|
|
return count;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static ssize_t amd64_inject_ecc_vector_show(struct device *dev,
|
|
struct device_attribute *mattr,
|
|
char *buf)
|
|
{
|
|
struct mem_ctl_info *mci = to_mci(dev);
|
|
struct amd64_pvt *pvt = mci->pvt_info;
|
|
return sprintf(buf, "0x%x\n", pvt->injection.bit_map);
|
|
}
|
|
|
|
/*
|
|
* store 16 bit error injection vector which enables injecting errors to the
|
|
* corresponding bit within the error injection word above. When used during a
|
|
* DRAM ECC read, it holds the contents of the of the DRAM ECC bits.
|
|
*/
|
|
static ssize_t amd64_inject_ecc_vector_store(struct device *dev,
|
|
struct device_attribute *mattr,
|
|
const char *data, size_t count)
|
|
{
|
|
struct mem_ctl_info *mci = to_mci(dev);
|
|
struct amd64_pvt *pvt = mci->pvt_info;
|
|
unsigned long value;
|
|
int ret = 0;
|
|
|
|
ret = strict_strtoul(data, 16, &value);
|
|
if (ret != -EINVAL) {
|
|
|
|
if (value & 0xFFFF0000) {
|
|
amd64_warn("%s: invalid EccVector: 0x%lx\n",
|
|
__func__, value);
|
|
return -EINVAL;
|
|
}
|
|
|
|
pvt->injection.bit_map = (u32) value;
|
|
return count;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Do a DRAM ECC read. Assemble staged values in the pvt area, format into
|
|
* fields needed by the injection registers and read the NB Array Data Port.
|
|
*/
|
|
static ssize_t amd64_inject_read_store(struct device *dev,
|
|
struct device_attribute *mattr,
|
|
const char *data, size_t count)
|
|
{
|
|
struct mem_ctl_info *mci = to_mci(dev);
|
|
struct amd64_pvt *pvt = mci->pvt_info;
|
|
unsigned long value;
|
|
u32 section, word_bits;
|
|
int ret = 0;
|
|
|
|
ret = strict_strtoul(data, 10, &value);
|
|
if (ret != -EINVAL) {
|
|
|
|
/* Form value to choose 16-byte section of cacheline */
|
|
section = F10_NB_ARRAY_DRAM_ECC |
|
|
SET_NB_ARRAY_ADDRESS(pvt->injection.section);
|
|
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
|
|
|
|
word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word,
|
|
pvt->injection.bit_map);
|
|
|
|
/* Issue 'word' and 'bit' along with the READ request */
|
|
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
|
|
|
|
edac_dbg(0, "section=0x%x word_bits=0x%x\n",
|
|
section, word_bits);
|
|
|
|
return count;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Do a DRAM ECC write. Assemble staged values in the pvt area and format into
|
|
* fields needed by the injection registers.
|
|
*/
|
|
static ssize_t amd64_inject_write_store(struct device *dev,
|
|
struct device_attribute *mattr,
|
|
const char *data, size_t count)
|
|
{
|
|
struct mem_ctl_info *mci = to_mci(dev);
|
|
struct amd64_pvt *pvt = mci->pvt_info;
|
|
unsigned long value;
|
|
u32 section, word_bits;
|
|
int ret = 0;
|
|
|
|
ret = strict_strtoul(data, 10, &value);
|
|
if (ret != -EINVAL) {
|
|
|
|
/* Form value to choose 16-byte section of cacheline */
|
|
section = F10_NB_ARRAY_DRAM_ECC |
|
|
SET_NB_ARRAY_ADDRESS(pvt->injection.section);
|
|
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
|
|
|
|
word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word,
|
|
pvt->injection.bit_map);
|
|
|
|
/* Issue 'word' and 'bit' along with the READ request */
|
|
amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
|
|
|
|
edac_dbg(0, "section=0x%x word_bits=0x%x\n",
|
|
section, word_bits);
|
|
|
|
return count;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* update NUM_INJ_ATTRS in case you add new members
|
|
*/
|
|
|
|
static DEVICE_ATTR(inject_section, S_IRUGO | S_IWUSR,
|
|
amd64_inject_section_show, amd64_inject_section_store);
|
|
static DEVICE_ATTR(inject_word, S_IRUGO | S_IWUSR,
|
|
amd64_inject_word_show, amd64_inject_word_store);
|
|
static DEVICE_ATTR(inject_ecc_vector, S_IRUGO | S_IWUSR,
|
|
amd64_inject_ecc_vector_show, amd64_inject_ecc_vector_store);
|
|
static DEVICE_ATTR(inject_write, S_IRUGO | S_IWUSR,
|
|
NULL, amd64_inject_write_store);
|
|
static DEVICE_ATTR(inject_read, S_IRUGO | S_IWUSR,
|
|
NULL, amd64_inject_read_store);
|
|
|
|
|
|
int amd64_create_sysfs_inject_files(struct mem_ctl_info *mci)
|
|
{
|
|
int rc;
|
|
|
|
rc = device_create_file(&mci->dev, &dev_attr_inject_section);
|
|
if (rc < 0)
|
|
return rc;
|
|
rc = device_create_file(&mci->dev, &dev_attr_inject_word);
|
|
if (rc < 0)
|
|
return rc;
|
|
rc = device_create_file(&mci->dev, &dev_attr_inject_ecc_vector);
|
|
if (rc < 0)
|
|
return rc;
|
|
rc = device_create_file(&mci->dev, &dev_attr_inject_write);
|
|
if (rc < 0)
|
|
return rc;
|
|
rc = device_create_file(&mci->dev, &dev_attr_inject_read);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void amd64_remove_sysfs_inject_files(struct mem_ctl_info *mci)
|
|
{
|
|
device_remove_file(&mci->dev, &dev_attr_inject_section);
|
|
device_remove_file(&mci->dev, &dev_attr_inject_word);
|
|
device_remove_file(&mci->dev, &dev_attr_inject_ecc_vector);
|
|
device_remove_file(&mci->dev, &dev_attr_inject_write);
|
|
device_remove_file(&mci->dev, &dev_attr_inject_read);
|
|
}
|