mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 03:05:29 +07:00
6c0afb5039
Currently, TI clock driver uses an encapsulated struct that is cast into a void pointer to store all register addresses. This can be considered as rather nasty hackery, and prevents from expanding the register address field also. Instead, replace all the code to use proper struct in place for this, which contains all the previously used data. This patch is rather large as it is touching multiple files, but this can't be split up as we need to avoid any boot breakage. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
661 lines
14 KiB
C
661 lines
14 KiB
C
/*
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* TI Divider Clock
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* Tero Kristo <t-kristo@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clk/ti.h>
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#include "clock.h"
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#undef pr_fmt
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#define div_mask(d) ((1 << ((d)->width)) - 1)
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static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
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{
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unsigned int maxdiv = 0;
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div > maxdiv)
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maxdiv = clkt->div;
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return maxdiv;
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}
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static unsigned int _get_maxdiv(struct clk_omap_divider *divider)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return div_mask(divider);
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return 1 << div_mask(divider);
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if (divider->table)
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return _get_table_maxdiv(divider->table);
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return div_mask(divider) + 1;
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}
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static unsigned int _get_table_div(const struct clk_div_table *table,
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unsigned int val)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->val == val)
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return clkt->div;
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return 0;
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}
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static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return val;
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return 1 << val;
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if (divider->table)
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return _get_table_div(divider->table, val);
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return val + 1;
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}
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static unsigned int _get_table_val(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return clkt->val;
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return 0;
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}
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static unsigned int _get_val(struct clk_omap_divider *divider, u8 div)
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{
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if (divider->flags & CLK_DIVIDER_ONE_BASED)
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return div;
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return __ffs(div);
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if (divider->table)
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return _get_table_val(divider->table, div);
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return div - 1;
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}
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static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_omap_divider *divider = to_clk_omap_divider(hw);
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unsigned int div, val;
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val = ti_clk_ll_ops->clk_readl(÷r->reg) >> divider->shift;
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val &= div_mask(divider);
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div = _get_div(divider, val);
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if (!div) {
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WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
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"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
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clk_hw_get_name(hw));
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return parent_rate;
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}
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return DIV_ROUND_UP(parent_rate, div);
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}
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/*
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* The reverse of DIV_ROUND_UP: The maximum number which
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* divided by m is r
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*/
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#define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
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static bool _is_valid_table_div(const struct clk_div_table *table,
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unsigned int div)
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{
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const struct clk_div_table *clkt;
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for (clkt = table; clkt->div; clkt++)
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if (clkt->div == div)
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return true;
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return false;
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}
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static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div)
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{
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if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
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return is_power_of_2(div);
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if (divider->table)
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return _is_valid_table_div(divider->table, div);
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return true;
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}
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static int _div_round_up(const struct clk_div_table *table,
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unsigned long parent_rate, unsigned long rate)
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{
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const struct clk_div_table *clkt;
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int up = INT_MAX;
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int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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for (clkt = table; clkt->div; clkt++) {
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if (clkt->div == div)
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return clkt->div;
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else if (clkt->div < div)
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continue;
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if ((clkt->div - div) < (up - div))
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up = clkt->div;
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}
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return up;
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}
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static int _div_round(const struct clk_div_table *table,
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unsigned long parent_rate, unsigned long rate)
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{
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if (!table)
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return DIV_ROUND_UP(parent_rate, rate);
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return _div_round_up(table, parent_rate, rate);
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}
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static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
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unsigned long *best_parent_rate)
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{
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struct clk_omap_divider *divider = to_clk_omap_divider(hw);
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int i, bestdiv = 0;
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unsigned long parent_rate, best = 0, now, maxdiv;
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unsigned long parent_rate_saved = *best_parent_rate;
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if (!rate)
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rate = 1;
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maxdiv = _get_maxdiv(divider);
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if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
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parent_rate = *best_parent_rate;
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bestdiv = _div_round(divider->table, parent_rate, rate);
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bestdiv = bestdiv == 0 ? 1 : bestdiv;
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bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
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return bestdiv;
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}
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/*
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* The maximum divider we can use without overflowing
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* unsigned long in rate * i below
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*/
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maxdiv = min(ULONG_MAX / rate, maxdiv);
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for (i = 1; i <= maxdiv; i++) {
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if (!_is_valid_div(divider, i))
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continue;
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if (rate * i == parent_rate_saved) {
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/*
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* It's the most ideal case if the requested rate can be
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* divided from parent clock without needing to change
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* parent rate, so return the divider immediately.
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*/
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*best_parent_rate = parent_rate_saved;
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return i;
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}
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parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
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MULT_ROUND_UP(rate, i));
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now = DIV_ROUND_UP(parent_rate, i);
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if (now <= rate && now > best) {
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bestdiv = i;
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best = now;
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*best_parent_rate = parent_rate;
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}
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}
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if (!bestdiv) {
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bestdiv = _get_maxdiv(divider);
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*best_parent_rate =
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clk_hw_round_rate(clk_hw_get_parent(hw), 1);
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}
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return bestdiv;
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}
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static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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int div;
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div = ti_clk_divider_bestdiv(hw, rate, prate);
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return DIV_ROUND_UP(*prate, div);
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}
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static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_omap_divider *divider;
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unsigned int div, value;
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u32 val;
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if (!hw || !rate)
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return -EINVAL;
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divider = to_clk_omap_divider(hw);
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div = DIV_ROUND_UP(parent_rate, rate);
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value = _get_val(divider, div);
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if (value > div_mask(divider))
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value = div_mask(divider);
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if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
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val = div_mask(divider) << (divider->shift + 16);
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} else {
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val = ti_clk_ll_ops->clk_readl(÷r->reg);
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val &= ~(div_mask(divider) << divider->shift);
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}
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val |= value << divider->shift;
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ti_clk_ll_ops->clk_writel(val, ÷r->reg);
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return 0;
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}
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const struct clk_ops ti_clk_divider_ops = {
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.recalc_rate = ti_clk_divider_recalc_rate,
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.round_rate = ti_clk_divider_round_rate,
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.set_rate = ti_clk_divider_set_rate,
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};
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static struct clk *_register_divider(struct device *dev, const char *name,
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const char *parent_name,
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unsigned long flags,
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struct clk_omap_reg *reg,
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u8 shift, u8 width, u8 clk_divider_flags,
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const struct clk_div_table *table)
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{
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struct clk_omap_divider *div;
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struct clk *clk;
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struct clk_init_data init;
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if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
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if (width + shift > 16) {
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pr_warn("divider value exceeds LOWORD field\n");
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return ERR_PTR(-EINVAL);
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}
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}
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/* allocate the divider */
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div) {
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pr_err("%s: could not allocate divider clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &ti_clk_divider_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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/* struct clk_divider assignments */
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memcpy(&div->reg, reg, sizeof(*reg));
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div->shift = shift;
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div->width = width;
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div->flags = clk_divider_flags;
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div->hw.init = &init;
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div->table = table;
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/* register the clock */
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clk = ti_clk_register(dev, &div->hw, name);
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if (IS_ERR(clk))
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kfree(div);
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return clk;
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}
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int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
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u8 flags, u8 *width,
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const struct clk_div_table **table)
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{
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int valid_div = 0;
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u32 val;
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int div;
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int i;
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struct clk_div_table *tmp;
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if (!div_table) {
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if (flags & CLKF_INDEX_STARTS_AT_ONE)
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val = 1;
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else
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val = 0;
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div = 1;
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while (div < max_div) {
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if (flags & CLKF_INDEX_POWER_OF_TWO)
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div <<= 1;
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else
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div++;
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val++;
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}
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*width = fls(val);
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*table = NULL;
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return 0;
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}
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i = 0;
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while (!num_dividers || i < num_dividers) {
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if (div_table[i] == -1)
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break;
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if (div_table[i])
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valid_div++;
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i++;
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}
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num_dividers = i;
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tmp = kzalloc(sizeof(*tmp) * (valid_div + 1), GFP_KERNEL);
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if (!tmp)
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return -ENOMEM;
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valid_div = 0;
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*width = 0;
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for (i = 0; i < num_dividers; i++)
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if (div_table[i] > 0) {
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tmp[valid_div].div = div_table[i];
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tmp[valid_div].val = i;
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valid_div++;
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*width = i;
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}
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*width = fls(*width);
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*table = tmp;
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return 0;
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}
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static const struct clk_div_table *
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_get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
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{
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const struct clk_div_table *table = NULL;
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ti_clk_parse_divider_data(setup->dividers, setup->num_dividers,
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setup->max_div, setup->flags, width,
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&table);
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return table;
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}
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struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
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{
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struct clk_omap_divider *div;
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struct clk_omap_reg *reg;
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if (!setup)
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return NULL;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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reg = (struct clk_omap_reg *)&div->reg;
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reg->index = setup->module;
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reg->offset = setup->reg;
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if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
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div->flags |= CLK_DIVIDER_ONE_BASED;
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if (setup->flags & CLKF_INDEX_POWER_OF_TWO)
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div->flags |= CLK_DIVIDER_POWER_OF_TWO;
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div->table = _get_div_table_from_setup(setup, &div->width);
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div->shift = setup->bit_shift;
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return &div->hw;
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}
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struct clk *ti_clk_register_divider(struct ti_clk *setup)
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{
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struct ti_clk_divider *div;
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struct clk_omap_reg *reg_setup;
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u32 reg;
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u8 width;
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u32 flags = 0;
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u8 div_flags = 0;
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const struct clk_div_table *table;
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struct clk *clk;
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div = setup->data;
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reg_setup = (struct clk_omap_reg *)®
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reg_setup->index = div->module;
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reg_setup->offset = div->reg;
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if (div->flags & CLKF_INDEX_STARTS_AT_ONE)
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div_flags |= CLK_DIVIDER_ONE_BASED;
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if (div->flags & CLKF_INDEX_POWER_OF_TWO)
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div_flags |= CLK_DIVIDER_POWER_OF_TWO;
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if (div->flags & CLKF_SET_RATE_PARENT)
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flags |= CLK_SET_RATE_PARENT;
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table = _get_div_table_from_setup(div, &width);
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if (IS_ERR(table))
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return (struct clk *)table;
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clk = _register_divider(NULL, setup->name, div->parent,
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flags, (void __iomem *)reg, div->bit_shift,
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width, div_flags, table);
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if (IS_ERR(clk))
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kfree(table);
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return clk;
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}
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static struct clk_div_table *
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__init ti_clk_get_div_table(struct device_node *node)
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{
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struct clk_div_table *table;
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const __be32 *divspec;
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u32 val;
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u32 num_div;
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u32 valid_div;
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int i;
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divspec = of_get_property(node, "ti,dividers", &num_div);
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if (!divspec)
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return NULL;
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num_div /= 4;
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valid_div = 0;
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/* Determine required size for divider table */
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for (i = 0; i < num_div; i++) {
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of_property_read_u32_index(node, "ti,dividers", i, &val);
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if (val)
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valid_div++;
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}
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if (!valid_div) {
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pr_err("no valid dividers for %s table\n", node->name);
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return ERR_PTR(-EINVAL);
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}
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table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL);
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if (!table)
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return ERR_PTR(-ENOMEM);
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valid_div = 0;
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for (i = 0; i < num_div; i++) {
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of_property_read_u32_index(node, "ti,dividers", i, &val);
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if (val) {
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table[valid_div].div = val;
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table[valid_div].val = i;
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valid_div++;
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}
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}
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return table;
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}
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static int _get_divider_width(struct device_node *node,
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const struct clk_div_table *table,
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u8 flags)
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{
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u32 min_div;
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u32 max_div;
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u32 val = 0;
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u32 div;
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if (!table) {
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/* Clk divider table not provided, determine min/max divs */
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if (of_property_read_u32(node, "ti,min-div", &min_div))
|
|
min_div = 1;
|
|
|
|
if (of_property_read_u32(node, "ti,max-div", &max_div)) {
|
|
pr_err("no max-div for %s!\n", node->name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Determine bit width for the field */
|
|
if (flags & CLK_DIVIDER_ONE_BASED)
|
|
val = 1;
|
|
|
|
div = min_div;
|
|
|
|
while (div < max_div) {
|
|
if (flags & CLK_DIVIDER_POWER_OF_TWO)
|
|
div <<= 1;
|
|
else
|
|
div++;
|
|
val++;
|
|
}
|
|
} else {
|
|
div = 0;
|
|
|
|
while (table[div].div) {
|
|
val = table[div].val;
|
|
div++;
|
|
}
|
|
}
|
|
|
|
return fls(val);
|
|
}
|
|
|
|
static int __init ti_clk_divider_populate(struct device_node *node,
|
|
struct clk_omap_reg *reg, const struct clk_div_table **table,
|
|
u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
|
|
{
|
|
u32 val;
|
|
int ret;
|
|
|
|
ret = ti_clk_get_reg_addr(node, 0, reg);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!of_property_read_u32(node, "ti,bit-shift", &val))
|
|
*shift = val;
|
|
else
|
|
*shift = 0;
|
|
|
|
*flags = 0;
|
|
*div_flags = 0;
|
|
|
|
if (of_property_read_bool(node, "ti,index-starts-at-one"))
|
|
*div_flags |= CLK_DIVIDER_ONE_BASED;
|
|
|
|
if (of_property_read_bool(node, "ti,index-power-of-two"))
|
|
*div_flags |= CLK_DIVIDER_POWER_OF_TWO;
|
|
|
|
if (of_property_read_bool(node, "ti,set-rate-parent"))
|
|
*flags |= CLK_SET_RATE_PARENT;
|
|
|
|
*table = ti_clk_get_div_table(node);
|
|
|
|
if (IS_ERR(*table))
|
|
return PTR_ERR(*table);
|
|
|
|
*width = _get_divider_width(node, *table, *div_flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* of_ti_divider_clk_setup - Setup function for simple div rate clock
|
|
* @node: device node for this clock
|
|
*
|
|
* Sets up a basic divider clock.
|
|
*/
|
|
static void __init of_ti_divider_clk_setup(struct device_node *node)
|
|
{
|
|
struct clk *clk;
|
|
const char *parent_name;
|
|
struct clk_omap_reg reg;
|
|
u8 clk_divider_flags = 0;
|
|
u8 width = 0;
|
|
u8 shift = 0;
|
|
const struct clk_div_table *table = NULL;
|
|
u32 flags = 0;
|
|
|
|
parent_name = of_clk_get_parent_name(node, 0);
|
|
|
|
if (ti_clk_divider_populate(node, ®, &table, &flags,
|
|
&clk_divider_flags, &width, &shift))
|
|
goto cleanup;
|
|
|
|
clk = _register_divider(NULL, node->name, parent_name, flags, ®,
|
|
shift, width, clk_divider_flags, table);
|
|
|
|
if (!IS_ERR(clk)) {
|
|
of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
|
of_ti_clk_autoidle_setup(node);
|
|
return;
|
|
}
|
|
|
|
cleanup:
|
|
kfree(table);
|
|
}
|
|
CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
|
|
|
|
static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
|
|
{
|
|
struct clk_omap_divider *div;
|
|
u32 val;
|
|
|
|
div = kzalloc(sizeof(*div), GFP_KERNEL);
|
|
if (!div)
|
|
return;
|
|
|
|
if (ti_clk_divider_populate(node, &div->reg, &div->table, &val,
|
|
&div->flags, &div->width, &div->shift) < 0)
|
|
goto cleanup;
|
|
|
|
if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER))
|
|
return;
|
|
|
|
cleanup:
|
|
kfree(div->table);
|
|
kfree(div);
|
|
}
|
|
CLK_OF_DECLARE(ti_composite_divider_clk, "ti,composite-divider-clock",
|
|
of_ti_composite_divider_clk_setup);
|