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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c1821c2e97
This provides a noexec protection on s390 hardware. Our hardware does not have any bits left in the pte for a hw noexec bit, so this is a different approach using shadow page tables and a special addressing mode that allows separate address spaces for code and data. As a special feature of our "secondary-space" addressing mode, separate page tables can be specified for the translation of data addresses (storage operands) and instruction addresses. The shadow page table is used for the instruction addresses and the standard page table for the data addresses. The shadow page table is linked to the standard page table by a pointer in page->lru.next of the struct page corresponding to the page that contains the standard page table (since page->private is not really private with the pte_lock and the page table pages are not in the LRU list). Depending on the software bits of a pte, it is either inserted into both page tables or just into the standard (data) page table. Pages of a vma that does not have the VM_EXEC bit set get mapped only in the data address space. Any try to execute code on such a page will cause a page translation exception. The standard reaction to this is a SIGSEGV with two exceptions: the two system call opcodes 0x0a77 (sys_sigreturn) and 0x0aad (sys_rt_sigreturn) are allowed. They are stored by the kernel to the signal stack frame. Unfortunately, the signal return mechanism cannot be modified to use an SA_RESTORER because the exception unwinding code depends on the system call opcode stored behind the signal stack frame. This feature requires that user space is executed in secondary-space mode and the kernel in home-space mode, which means that the addressing modes need to be switched and that the noexec protection only works for user space. After switching the addressing modes, we cannot use the mvcp/mvcs instructions anymore to copy between kernel and user space. A new mvcos instruction has been added to the z9 EC/BC hardware which allows to copy between arbitrary address spaces, but on older hardware the page tables need to be walked manually. Signed-off-by: Gerald Schaefer <geraldsc@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
162 lines
3.7 KiB
C
162 lines
3.7 KiB
C
#ifndef _S390_TLBFLUSH_H
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#define _S390_TLBFLUSH_H
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#include <linux/mm.h>
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#include <asm/processor.h>
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#include <asm/pgalloc.h>
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/*
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* TLB flushing:
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*
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* - flush_tlb() flushes the current mm struct TLBs
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* - flush_tlb_all() flushes all processes TLBs
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* - flush_tlb_mm(mm) flushes the specified mm context TLB's
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* - flush_tlb_page(vma, vmaddr) flushes one page
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* - flush_tlb_range(vma, start, end) flushes a range of pages
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* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
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* - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
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*/
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/*
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* S/390 has three ways of flushing TLBs
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* 'ptlb' does a flush of the local processor
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* 'csp' flushes the TLBs on all PUs of a SMP
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* 'ipte' invalidates a pte in a page table and flushes that out of
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* the TLBs of all PUs of a SMP
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*/
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#define local_flush_tlb() \
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do { asm volatile("ptlb": : :"memory"); } while (0)
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#ifndef CONFIG_SMP
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/*
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* We always need to flush, since s390 does not flush tlb
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* on each context switch
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*/
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static inline void flush_tlb(void)
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{
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local_flush_tlb();
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}
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static inline void flush_tlb_all(void)
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{
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local_flush_tlb();
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}
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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local_flush_tlb();
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long addr)
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{
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local_flush_tlb();
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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local_flush_tlb();
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}
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#define flush_tlb_kernel_range(start, end) \
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local_flush_tlb();
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#else
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#include <asm/smp.h>
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extern void smp_ptlb_all(void);
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static inline void global_flush_tlb(void)
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{
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register unsigned long reg2 asm("2");
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register unsigned long reg3 asm("3");
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register unsigned long reg4 asm("4");
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long dummy;
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#ifndef __s390x__
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if (!MACHINE_HAS_CSP) {
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smp_ptlb_all();
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return;
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}
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#endif /* __s390x__ */
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dummy = 0;
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reg2 = reg3 = 0;
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reg4 = ((unsigned long) &dummy) + 1;
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asm volatile(
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" csp %0,%2"
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: : "d" (reg2), "d" (reg3), "d" (reg4), "m" (dummy) : "cc" );
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}
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/*
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* We only have to do global flush of tlb if process run since last
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* flush on any other pu than current.
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* If we have threads (mm->count > 1) we always do a global flush,
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* since the process runs on more than one processor at the same time.
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*/
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static inline void __flush_tlb_mm(struct mm_struct * mm)
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{
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cpumask_t local_cpumask;
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if (unlikely(cpus_empty(mm->cpu_vm_mask)))
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return;
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if (MACHINE_HAS_IDTE) {
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pgd_t *shadow_pgd = get_shadow_pgd(mm->pgd);
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if (shadow_pgd) {
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asm volatile(
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" .insn rrf,0xb98e0000,0,%0,%1,0"
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: : "a" (2048),
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"a" (__pa(shadow_pgd) & PAGE_MASK) : "cc" );
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}
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asm volatile(
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" .insn rrf,0xb98e0000,0,%0,%1,0"
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: : "a" (2048), "a" (__pa(mm->pgd)&PAGE_MASK) : "cc");
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return;
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}
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preempt_disable();
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local_cpumask = cpumask_of_cpu(smp_processor_id());
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if (cpus_equal(mm->cpu_vm_mask, local_cpumask))
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local_flush_tlb();
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else
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global_flush_tlb();
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preempt_enable();
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}
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static inline void flush_tlb(void)
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{
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__flush_tlb_mm(current->mm);
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}
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static inline void flush_tlb_all(void)
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{
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global_flush_tlb();
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}
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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__flush_tlb_mm(mm);
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long addr)
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{
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__flush_tlb_mm(vma->vm_mm);
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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__flush_tlb_mm(vma->vm_mm);
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}
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#define flush_tlb_kernel_range(start, end) global_flush_tlb()
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#endif
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static inline void flush_tlb_pgtables(struct mm_struct *mm,
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unsigned long start, unsigned long end)
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{
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/* S/390 does not keep any page table caches in TLB */
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}
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#endif /* _S390_TLBFLUSH_H */
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