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35780e860f
According to "KeyStone Architecture Inter-IC Control Bus User Guide", fixed
additive part of frequency divisors (referred as "d" in the code and datasheet)
always equals to 6, independent of module clock prescaler.
module clock frequency
master clock frequency = ----------------------
(ICCL + 6) + (ICCH + 6)
It was not the case with original Davinci IP. Introduce new compatible property
"ti,keystone-i2c", which triggers special handling in the driver.
Without this change Keystone-based systems (having 204.8MHz input clock) choose
prescaler 29 (PSC=28). Using d=5 in this case leads to bus bitrate ~353kHz
instead of requested 400kHz. After correction, assuming d=6 bus rate is ~392kHz.
This gives ~11% transfer rate increase.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Tested-by: Hemanth Guruva Reddy <hemanth.guruva_reddy@nokia.com>
Tested-by: Lukasz Gemborowski <lukasz.gemborowski@nokia.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
32 lines
890 B
Plaintext
32 lines
890 B
Plaintext
* Texas Instruments Davinci/Keystone I2C
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This file provides information, what the device node for the
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davinci/keystone i2c interface contains.
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Required properties:
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- compatible: "ti,davinci-i2c" or "ti,keystone-i2c";
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- reg : Offset and length of the register set for the device
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Recommended properties :
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- interrupts : standard interrupt property.
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- clock-frequency : desired I2C bus clock frequency in Hz.
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- ti,has-pfunc: boolean; if defined, it indicates that SoC supports PFUNC
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registers. PFUNC registers allow to switch I2C pins to function as
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GPIOs, so they can by toggled manually.
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Example (enbw_cmc board):
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i2c@1c22000 {
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compatible = "ti,davinci-i2c";
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reg = <0x22000 0x1000>;
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clock-frequency = <100000>;
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interrupts = <15>;
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interrupt-parent = <&intc>;
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#address-cells = <1>;
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#size-cells = <0>;
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dtt@48 {
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compatible = "national,lm75";
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reg = <0x48>;
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};
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};
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