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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 01:56:40 +07:00
b6e0e8c077
This patch adds support for multi-chip NAND devices to the FSL-UPM driver. This requires support for multiple GPIOs for the RNB pins. The NAND chips are selected through address lines defined by the FDT property "fsl,upm-addr-line-cs-offsets". Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
175 lines
3.9 KiB
C
175 lines
3.9 KiB
C
/*
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* Freescale LBC and UPM routines.
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*
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* Copyright (c) 2007-2008 MontaVista Software, Inc.
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*
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* Author: Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <asm/prom.h>
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#include <asm/fsl_lbc.h>
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static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
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static struct fsl_lbc_regs __iomem *fsl_lbc_regs;
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static char __initdata *compat_lbc[] = {
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"fsl,pq2-localbus",
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"fsl,pq2pro-localbus",
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"fsl,pq3-localbus",
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"fsl,elbc",
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};
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static int __init fsl_lbc_init(void)
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{
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struct device_node *lbus;
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int i;
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for (i = 0; i < ARRAY_SIZE(compat_lbc); i++) {
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lbus = of_find_compatible_node(NULL, NULL, compat_lbc[i]);
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if (lbus)
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goto found;
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}
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return -ENODEV;
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found:
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fsl_lbc_regs = of_iomap(lbus, 0);
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of_node_put(lbus);
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if (!fsl_lbc_regs)
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return -ENOMEM;
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return 0;
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}
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arch_initcall(fsl_lbc_init);
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/**
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* fsl_lbc_find - find Localbus bank
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* @addr_base: base address of the memory bank
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*
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* This function walks LBC banks comparing "Base address" field of the BR
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* registers with the supplied addr_base argument. When bases match this
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* function returns bank number (starting with 0), otherwise it returns
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* appropriate errno value.
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*/
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int fsl_lbc_find(phys_addr_t addr_base)
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{
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int i;
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if (!fsl_lbc_regs)
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return -ENODEV;
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for (i = 0; i < ARRAY_SIZE(fsl_lbc_regs->bank); i++) {
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__be32 br = in_be32(&fsl_lbc_regs->bank[i].br);
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__be32 or = in_be32(&fsl_lbc_regs->bank[i].or);
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if (br & BR_V && (br & or & BR_BA) == addr_base)
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return i;
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}
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return -ENOENT;
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}
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EXPORT_SYMBOL(fsl_lbc_find);
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/**
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* fsl_upm_find - find pre-programmed UPM via base address
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* @addr_base: base address of the memory bank controlled by the UPM
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* @upm: pointer to the allocated fsl_upm structure
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*
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* This function fills fsl_upm structure so you can use it with the rest of
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* UPM API. On success this function returns 0, otherwise it returns
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* appropriate errno value.
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*/
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int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
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{
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int bank;
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__be32 br;
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bank = fsl_lbc_find(addr_base);
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if (bank < 0)
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return bank;
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br = in_be32(&fsl_lbc_regs->bank[bank].br);
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switch (br & BR_MSEL) {
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case BR_MS_UPMA:
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upm->mxmr = &fsl_lbc_regs->mamr;
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break;
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case BR_MS_UPMB:
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upm->mxmr = &fsl_lbc_regs->mbmr;
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break;
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case BR_MS_UPMC:
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upm->mxmr = &fsl_lbc_regs->mcmr;
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break;
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default:
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return -EINVAL;
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}
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switch (br & BR_PS) {
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case BR_PS_8:
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upm->width = 8;
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break;
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case BR_PS_16:
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upm->width = 16;
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break;
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case BR_PS_32:
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upm->width = 32;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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EXPORT_SYMBOL(fsl_upm_find);
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/**
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* fsl_upm_run_pattern - actually run an UPM pattern
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* @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
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* @io_base: remapped pointer to where memory access should happen
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* @mar: MAR register content during pattern execution
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*
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* This function triggers dummy write to the memory specified by the io_base,
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* thus UPM pattern actually executed. Note that mar usage depends on the
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* pre-programmed AMX bits in the UPM RAM.
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*/
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int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
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{
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int ret = 0;
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unsigned long flags;
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spin_lock_irqsave(&fsl_lbc_lock, flags);
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out_be32(&fsl_lbc_regs->mar, mar);
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switch (upm->width) {
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case 8:
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out_8(io_base, 0x0);
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break;
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case 16:
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out_be16(io_base, 0x0);
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break;
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case 32:
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out_be32(io_base, 0x0);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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spin_unlock_irqrestore(&fsl_lbc_lock, flags);
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return ret;
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}
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EXPORT_SYMBOL(fsl_upm_run_pattern);
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