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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
100 lines
2.4 KiB
C
100 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* drivers/soc/fsl/qe/qe_ic.h
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*
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* QUICC ENGINE Interrupt Controller Header
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*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: Li Yang <leoli@freescale.com>
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* Based on code from Shlomi Gridish <gridish@freescale.com>
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*/
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#ifndef _POWERPC_SYSDEV_QE_IC_H
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#define _POWERPC_SYSDEV_QE_IC_H
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#include <soc/fsl/qe/qe_ic.h>
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#define NR_QE_IC_INTS 64
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/* QE IC registers offset */
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#define QEIC_CICR 0x00
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#define QEIC_CIVEC 0x04
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#define QEIC_CRIPNR 0x08
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#define QEIC_CIPNR 0x0c
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#define QEIC_CIPXCC 0x10
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#define QEIC_CIPYCC 0x14
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#define QEIC_CIPWCC 0x18
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#define QEIC_CIPZCC 0x1c
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#define QEIC_CIMR 0x20
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#define QEIC_CRIMR 0x24
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#define QEIC_CICNR 0x28
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#define QEIC_CIPRTA 0x30
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#define QEIC_CIPRTB 0x34
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#define QEIC_CRICR 0x3c
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#define QEIC_CHIVEC 0x60
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/* Interrupt priority registers */
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#define CIPCC_SHIFT_PRI0 29
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#define CIPCC_SHIFT_PRI1 26
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#define CIPCC_SHIFT_PRI2 23
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#define CIPCC_SHIFT_PRI3 20
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#define CIPCC_SHIFT_PRI4 13
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#define CIPCC_SHIFT_PRI5 10
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#define CIPCC_SHIFT_PRI6 7
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#define CIPCC_SHIFT_PRI7 4
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/* CICR priority modes */
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#define CICR_GWCC 0x00040000
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#define CICR_GXCC 0x00020000
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#define CICR_GYCC 0x00010000
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#define CICR_GZCC 0x00080000
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#define CICR_GRTA 0x00200000
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#define CICR_GRTB 0x00400000
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#define CICR_HPIT_SHIFT 8
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#define CICR_HPIT_MASK 0x00000300
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#define CICR_HP_SHIFT 24
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#define CICR_HP_MASK 0x3f000000
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/* CICNR */
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#define CICNR_WCC1T_SHIFT 20
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#define CICNR_ZCC1T_SHIFT 28
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#define CICNR_YCC1T_SHIFT 12
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#define CICNR_XCC1T_SHIFT 4
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/* CRICR */
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#define CRICR_RTA1T_SHIFT 20
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#define CRICR_RTB1T_SHIFT 28
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/* Signal indicator */
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#define SIGNAL_MASK 3
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#define SIGNAL_HIGH 2
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#define SIGNAL_LOW 0
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struct qe_ic {
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/* Control registers offset */
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volatile u32 __iomem *regs;
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/* The remapper for this QEIC */
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struct irq_domain *irqhost;
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/* The "linux" controller struct */
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struct irq_chip hc_irq;
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/* VIRQ numbers of QE high/low irqs */
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unsigned int virq_high;
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unsigned int virq_low;
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};
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/*
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* QE interrupt controller internal structure
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*/
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struct qe_ic_info {
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u32 mask; /* location of this source at the QIMR register. */
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u32 mask_reg; /* Mask register offset */
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u8 pri_code; /* for grouped interrupts sources - the interrupt
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code as appears at the group priority register */
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u32 pri_reg; /* Group priority register offset */
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};
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#endif /* _POWERPC_SYSDEV_QE_IC_H */
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