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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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722fb61e2e
TMIO_MMC_HAVE_HIGH_REG is confusing due to its counter-intuitive name. All the TMIO MMC variants (TMIO MMC, Renesas SDHI, UniPhier SD) actually have high registers. It is just that each of them implements its own registers there. The original IP from Panasonic only defines registers 0x00-0xff in the bus_shift=1 review. The register area above them is platform-dependent. In fact, TMIO_MMC_HAVE_HIGH_REG is set only by tmio-mmc.c and used to test the accessibility of CTL_SDIO_REGS. Because it is specific to the TMIO MFD variant, the right thing to do is to move such registers to tmio_mmc.c and delete the TMIO_MMC_HAVE_HIGH_REG flag. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
143 lines
3.9 KiB
C
143 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef MFD_TMIO_H
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#define MFD_TMIO_H
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#include <linux/device.h>
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#include <linux/fb.h>
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#include <linux/io.h>
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#include <linux/jiffies.h>
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#include <linux/mmc/card.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#define tmio_ioread8(addr) readb(addr)
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#define tmio_ioread16(addr) readw(addr)
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#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
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#define tmio_ioread32(addr) \
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(((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16))
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#define tmio_iowrite8(val, addr) writeb((val), (addr))
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#define tmio_iowrite16(val, addr) writew((val), (addr))
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#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
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#define tmio_iowrite32(val, addr) \
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do { \
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writew((val), (addr)); \
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writew((val) >> 16, (addr) + 2); \
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} while (0)
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#define sd_config_write8(base, shift, reg, val) \
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tmio_iowrite8((val), (base) + ((reg) << (shift)))
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#define sd_config_write16(base, shift, reg, val) \
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tmio_iowrite16((val), (base) + ((reg) << (shift)))
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#define sd_config_write32(base, shift, reg, val) \
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do { \
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tmio_iowrite16((val), (base) + ((reg) << (shift))); \
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tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
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} while (0)
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/* tmio MMC platform flags */
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/*
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* Some controllers can support a 2-byte block size when the bus width
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* is configured in 4-bit mode.
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*/
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#define TMIO_MMC_BLKSZ_2BYTES BIT(1)
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/*
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* Some controllers can support SDIO IRQ signalling.
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*/
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#define TMIO_MMC_SDIO_IRQ BIT(2)
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/* Some features are only available or tested on R-Car Gen2 or later */
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#define TMIO_MMC_MIN_RCAR2 BIT(3)
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/*
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* Some controllers require waiting for the SD bus to become
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* idle before writing to some registers.
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*/
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#define TMIO_MMC_HAS_IDLE_WAIT BIT(4)
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/*
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* A GPIO is used for card hotplug detection. We need an extra flag for this,
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* because 0 is a valid GPIO number too, and requiring users to specify
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* cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
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*/
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#define TMIO_MMC_USE_GPIO_CD BIT(5)
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/*
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* Some controllers have CMD12 automatically
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* issue/non-issue register
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*/
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#define TMIO_MMC_HAVE_CMD12_CTRL BIT(7)
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/* Controller has some SDIO status bits which must be 1 */
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#define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8)
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/*
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* Some controllers have a 32-bit wide data port register
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*/
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#define TMIO_MMC_32BIT_DATA_PORT BIT(9)
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/*
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* Some controllers allows to set SDx actual clock
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*/
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#define TMIO_MMC_CLK_ACTUAL BIT(10)
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/* Some controllers have a CBSY bit */
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#define TMIO_MMC_HAVE_CBSY BIT(11)
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/* Some controllers that support HS400 use use 4 taps while others use 8. */
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#define TMIO_MMC_HAVE_4TAP_HS400 BIT(13)
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int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
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int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
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void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
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void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
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struct dma_chan;
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/*
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* data for the MMC controller
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*/
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struct tmio_mmc_data {
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void *chan_priv_tx;
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void *chan_priv_rx;
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unsigned int hclk;
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unsigned long capabilities;
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unsigned long capabilities2;
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unsigned long flags;
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u32 ocr_mask; /* available voltages */
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unsigned int cd_gpio;
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int alignment_shift;
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dma_addr_t dma_rx_offset;
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unsigned int max_blk_count;
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unsigned short max_segs;
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void (*set_pwr)(struct platform_device *host, int state);
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void (*set_clk_div)(struct platform_device *host, int state);
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};
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/*
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* data for the NAND controller
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*/
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struct tmio_nand_data {
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struct nand_bbt_descr *badblock_pattern;
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struct mtd_partition *partition;
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unsigned int num_partitions;
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const char *const *part_parsers;
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};
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#define FBIO_TMIO_ACC_WRITE 0x7C639300
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#define FBIO_TMIO_ACC_SYNC 0x7C639301
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struct tmio_fb_data {
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int (*lcd_set_power)(struct platform_device *fb_dev,
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bool on);
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int (*lcd_mode)(struct platform_device *fb_dev,
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const struct fb_videomode *mode);
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int num_modes;
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struct fb_videomode *modes;
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/* in mm: size of screen */
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int height;
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int width;
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};
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#endif
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