mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d411a9368b
This change merges the ixgbe_cache_ring_fcoe and ixgbe_set_fcoe_queues logic into the DCB and RSS initialization calls. Cc: John Fastabend <john.r.fastabend@intel.com> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
869 lines
23 KiB
C
869 lines
23 KiB
C
/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2012 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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#include "ixgbe.h"
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#include "ixgbe_sriov.h"
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#ifdef CONFIG_IXGBE_DCB
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/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
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static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
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unsigned int *tx, unsigned int *rx)
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{
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struct net_device *dev = adapter->netdev;
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struct ixgbe_hw *hw = &adapter->hw;
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u8 num_tcs = netdev_get_num_tc(dev);
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*tx = 0;
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*rx = 0;
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switch (hw->mac.type) {
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case ixgbe_mac_82598EB:
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*tx = tc << 2;
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*rx = tc << 3;
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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if (num_tcs > 4) {
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if (tc < 3) {
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*tx = tc << 5;
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*rx = tc << 4;
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} else if (tc < 5) {
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*tx = ((tc + 2) << 4);
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*rx = tc << 4;
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} else if (tc < num_tcs) {
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*tx = ((tc + 8) << 3);
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*rx = tc << 4;
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}
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} else {
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*rx = tc << 5;
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switch (tc) {
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case 0:
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*tx = 0;
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break;
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case 1:
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*tx = 64;
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break;
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case 2:
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*tx = 96;
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break;
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case 3:
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*tx = 112;
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break;
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default:
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break;
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}
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}
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break;
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default:
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break;
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}
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}
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/**
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* ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
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* @adapter: board private structure to initialize
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*
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* Cache the descriptor ring offsets for DCB to the assigned rings.
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*
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**/
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static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
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{
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struct net_device *dev = adapter->netdev;
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int i, j, k;
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u8 num_tcs = netdev_get_num_tc(dev);
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if (!num_tcs)
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return false;
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for (i = 0, k = 0; i < num_tcs; i++) {
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unsigned int tx_s, rx_s;
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u16 count = dev->tc_to_txq[i].count;
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ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
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for (j = 0; j < count; j++, k++) {
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adapter->tx_ring[k]->reg_idx = tx_s + j;
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adapter->rx_ring[k]->reg_idx = rx_s + j;
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adapter->tx_ring[k]->dcb_tc = i;
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adapter->rx_ring[k]->dcb_tc = i;
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}
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}
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return true;
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}
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#endif
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/**
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* ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
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* @adapter: board private structure to initialize
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*
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* SR-IOV doesn't use any descriptor rings but changes the default if
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* no other mapping is used.
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*
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*/
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static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
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{
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adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
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adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
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if (adapter->num_vfs)
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return true;
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else
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return false;
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}
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/**
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* ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
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* @adapter: board private structure to initialize
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*
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* Cache the descriptor ring offsets for RSS to the assigned rings.
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*
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**/
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static bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
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{
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int i;
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if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
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return false;
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for (i = 0; i < adapter->num_rx_queues; i++)
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adapter->rx_ring[i]->reg_idx = i;
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for (i = 0; i < adapter->num_tx_queues; i++)
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adapter->tx_ring[i]->reg_idx = i;
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return true;
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}
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/**
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* ixgbe_cache_ring_register - Descriptor ring to register mapping
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* @adapter: board private structure to initialize
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*
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* Once we know the feature-set enabled for the device, we'll cache
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* the register offset the descriptor ring is assigned to.
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*
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* Note, the order the various feature calls is important. It must start with
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* the "most" features enabled at the same time, then trickle down to the
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* least amount of features turned on at once.
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**/
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static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
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{
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/* start with default case */
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adapter->rx_ring[0]->reg_idx = 0;
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adapter->tx_ring[0]->reg_idx = 0;
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if (ixgbe_cache_ring_sriov(adapter))
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return;
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#ifdef CONFIG_IXGBE_DCB
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if (ixgbe_cache_ring_dcb(adapter))
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return;
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#endif
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ixgbe_cache_ring_rss(adapter);
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}
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/**
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* ixgbe_set_sriov_queues - Allocate queues for IOV use
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* @adapter: board private structure to initialize
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*
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* IOV doesn't actually use anything, so just NAK the
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* request for now and let the other queue routines
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* figure out what to do.
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*/
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static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
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{
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return false;
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}
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#define IXGBE_RSS_16Q_MASK 0xF
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#define IXGBE_RSS_8Q_MASK 0x7
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#define IXGBE_RSS_4Q_MASK 0x3
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#define IXGBE_RSS_2Q_MASK 0x1
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#define IXGBE_RSS_DISABLED_MASK 0x0
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#ifdef CONFIG_IXGBE_DCB
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static bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
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{
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struct net_device *dev = adapter->netdev;
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struct ixgbe_ring_feature *f;
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int rss_i, rss_m, i;
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int tcs;
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/* Map queue offset and counts onto allocated tx queues */
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tcs = netdev_get_num_tc(dev);
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/* verify we have DCB queueing enabled before proceeding */
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if (tcs <= 1)
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return false;
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/* determine the upper limit for our current DCB mode */
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rss_i = dev->num_tx_queues / tcs;
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if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
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/* 8 TC w/ 4 queues per TC */
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rss_i = min_t(u16, rss_i, 4);
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rss_m = IXGBE_RSS_4Q_MASK;
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} else if (tcs > 4) {
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/* 8 TC w/ 8 queues per TC */
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rss_i = min_t(u16, rss_i, 8);
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rss_m = IXGBE_RSS_8Q_MASK;
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} else {
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/* 4 TC w/ 16 queues per TC */
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rss_i = min_t(u16, rss_i, 16);
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rss_m = IXGBE_RSS_16Q_MASK;
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}
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/* set RSS mask and indices */
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f = &adapter->ring_feature[RING_F_RSS];
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rss_i = min_t(int, rss_i, f->limit);
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f->indices = rss_i;
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f->mask = rss_m;
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#ifdef IXGBE_FCOE
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/* FCoE enabled queues require special configuration indexed
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* by feature specific indices and offset. Here we map FCoE
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* indices onto the DCB queue pairs allowing FCoE to own
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* configuration later.
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*/
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if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
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u8 tc = ixgbe_fcoe_get_tc(adapter);
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f = &adapter->ring_feature[RING_F_FCOE];
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f->indices = min_t(u16, rss_i, f->limit);
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f->offset = rss_i * tc;
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}
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#endif /* IXGBE_FCOE */
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for (i = 0; i < tcs; i++)
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netdev_set_tc_queue(dev, i, rss_i, rss_i * i);
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adapter->num_tx_queues = rss_i * tcs;
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adapter->num_rx_queues = rss_i * tcs;
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return true;
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}
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#endif
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/**
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* ixgbe_set_rss_queues - Allocate queues for RSS
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* @adapter: board private structure to initialize
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*
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* This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
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* to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
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*
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**/
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static bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
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{
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struct ixgbe_ring_feature *f;
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u16 rss_i;
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if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
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adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
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return false;
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}
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/* set mask for 16 queue limit of RSS */
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f = &adapter->ring_feature[RING_F_RSS];
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rss_i = f->limit;
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f->indices = rss_i;
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f->mask = IXGBE_RSS_16Q_MASK;
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/*
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* Use Flow Director in addition to RSS to ensure the best
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* distribution of flows across cores, even when an FDIR flow
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* isn't matched.
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*/
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if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
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f = &adapter->ring_feature[RING_F_FDIR];
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f->indices = min_t(u16, num_online_cpus(), f->limit);
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rss_i = max_t(u16, rss_i, f->indices);
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}
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#ifdef IXGBE_FCOE
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/*
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* FCoE can exist on the same rings as standard network traffic
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* however it is preferred to avoid that if possible. In order
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* to get the best performance we allocate as many FCoE queues
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* as we can and we place them at the end of the ring array to
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* avoid sharing queues with standard RSS on systems with 24 or
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* more CPUs.
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*/
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if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
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struct net_device *dev = adapter->netdev;
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u16 fcoe_i;
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f = &adapter->ring_feature[RING_F_FCOE];
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/* merge FCoE queues with RSS queues */
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fcoe_i = min_t(u16, f->limit + rss_i, num_online_cpus());
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fcoe_i = min_t(u16, fcoe_i, dev->num_tx_queues);
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/* limit indices to rss_i if MSI-X is disabled */
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if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
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fcoe_i = rss_i;
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/* attempt to reserve some queues for just FCoE */
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f->indices = min_t(u16, fcoe_i, f->limit);
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f->offset = fcoe_i - f->indices;
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rss_i = max_t(u16, fcoe_i, rss_i);
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}
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#endif /* IXGBE_FCOE */
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adapter->num_rx_queues = rss_i;
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adapter->num_tx_queues = rss_i;
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return true;
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}
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/**
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* ixgbe_set_num_queues - Allocate queues for device, feature dependent
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* @adapter: board private structure to initialize
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*
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* This is the top level queue allocation routine. The order here is very
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* important, starting with the "most" number of features turned on at once,
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* and ending with the smallest set of features. This way large combinations
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* can be allocated if they're turned on, and smaller combinations are the
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* fallthrough conditions.
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*
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**/
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static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
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{
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/* Start with base case */
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adapter->num_rx_queues = 1;
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adapter->num_tx_queues = 1;
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adapter->num_rx_pools = adapter->num_rx_queues;
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adapter->num_rx_queues_per_pool = 1;
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if (ixgbe_set_sriov_queues(adapter))
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goto done;
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#ifdef CONFIG_IXGBE_DCB
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if (ixgbe_set_dcb_queues(adapter))
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goto done;
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#endif
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if (ixgbe_set_rss_queues(adapter))
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goto done;
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/* fallback to base case */
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adapter->num_rx_queues = 1;
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adapter->num_tx_queues = 1;
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done:
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if ((adapter->netdev->reg_state == NETREG_UNREGISTERED) ||
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(adapter->netdev->reg_state == NETREG_UNREGISTERING))
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return 0;
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/* Notify the stack of the (possibly) reduced queue counts. */
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netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
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return netif_set_real_num_rx_queues(adapter->netdev,
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adapter->num_rx_queues);
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}
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static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
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int vectors)
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{
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int err, vector_threshold;
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/* We'll want at least 2 (vector_threshold):
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* 1) TxQ[0] + RxQ[0] handler
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* 2) Other (Link Status Change, etc.)
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*/
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vector_threshold = MIN_MSIX_COUNT;
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/*
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* The more we get, the more we will assign to Tx/Rx Cleanup
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* for the separate queues...where Rx Cleanup >= Tx Cleanup.
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* Right now, we simply care about how many we'll get; we'll
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* set them up later while requesting irq's.
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*/
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while (vectors >= vector_threshold) {
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err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
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vectors);
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if (!err) /* Success in acquiring all requested vectors. */
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break;
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else if (err < 0)
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vectors = 0; /* Nasty failure, quit now */
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else /* err == number of vectors we should try again with */
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vectors = err;
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}
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if (vectors < vector_threshold) {
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/* Can't allocate enough MSI-X interrupts? Oh well.
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* This just means we'll go with either a single MSI
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* vector or fall back to legacy interrupts.
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*/
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netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
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"Unable to allocate MSI-X interrupts\n");
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adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
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kfree(adapter->msix_entries);
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adapter->msix_entries = NULL;
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} else {
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adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
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/*
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* Adjust for only the vectors we'll use, which is minimum
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* of max_msix_q_vectors + NON_Q_VECTORS, or the number of
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* vectors we were allocated.
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*/
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vectors -= NON_Q_VECTORS;
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adapter->num_q_vectors = min(vectors, adapter->max_q_vectors);
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}
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}
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static void ixgbe_add_ring(struct ixgbe_ring *ring,
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struct ixgbe_ring_container *head)
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{
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ring->next = head->ring;
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head->ring = ring;
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head->count++;
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}
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/**
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* ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector
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* @adapter: board private structure to initialize
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* @v_count: q_vectors allocated on adapter, used for ring interleaving
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* @v_idx: index of vector in adapter struct
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* @txr_count: total number of Tx rings to allocate
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* @txr_idx: index of first Tx ring to allocate
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* @rxr_count: total number of Rx rings to allocate
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* @rxr_idx: index of first Rx ring to allocate
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*
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* We allocate one q_vector. If allocation fails we return -ENOMEM.
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**/
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static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter,
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int v_count, int v_idx,
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int txr_count, int txr_idx,
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int rxr_count, int rxr_idx)
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{
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struct ixgbe_q_vector *q_vector;
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struct ixgbe_ring *ring;
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int node = -1;
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int cpu = -1;
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int ring_count, size;
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ring_count = txr_count + rxr_count;
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size = sizeof(struct ixgbe_q_vector) +
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(sizeof(struct ixgbe_ring) * ring_count);
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/* customize cpu for Flow Director mapping */
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if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
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if (cpu_online(v_idx)) {
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cpu = v_idx;
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node = cpu_to_node(cpu);
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}
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}
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/* allocate q_vector and rings */
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q_vector = kzalloc_node(size, GFP_KERNEL, node);
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if (!q_vector)
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q_vector = kzalloc(size, GFP_KERNEL);
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if (!q_vector)
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return -ENOMEM;
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|
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/* setup affinity mask and node */
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if (cpu != -1)
|
|
cpumask_set_cpu(cpu, &q_vector->affinity_mask);
|
|
else
|
|
cpumask_copy(&q_vector->affinity_mask, cpu_online_mask);
|
|
q_vector->numa_node = node;
|
|
|
|
/* initialize NAPI */
|
|
netif_napi_add(adapter->netdev, &q_vector->napi,
|
|
ixgbe_poll, 64);
|
|
|
|
/* tie q_vector and adapter together */
|
|
adapter->q_vector[v_idx] = q_vector;
|
|
q_vector->adapter = adapter;
|
|
q_vector->v_idx = v_idx;
|
|
|
|
/* initialize work limits */
|
|
q_vector->tx.work_limit = adapter->tx_work_limit;
|
|
|
|
/* initialize pointer to rings */
|
|
ring = q_vector->ring;
|
|
|
|
while (txr_count) {
|
|
/* assign generic ring traits */
|
|
ring->dev = &adapter->pdev->dev;
|
|
ring->netdev = adapter->netdev;
|
|
|
|
/* configure backlink on ring */
|
|
ring->q_vector = q_vector;
|
|
|
|
/* update q_vector Tx values */
|
|
ixgbe_add_ring(ring, &q_vector->tx);
|
|
|
|
/* apply Tx specific ring traits */
|
|
ring->count = adapter->tx_ring_count;
|
|
ring->queue_index = txr_idx;
|
|
|
|
/* assign ring to adapter */
|
|
adapter->tx_ring[txr_idx] = ring;
|
|
|
|
/* update count and index */
|
|
txr_count--;
|
|
txr_idx += v_count;
|
|
|
|
/* push pointer to next ring */
|
|
ring++;
|
|
}
|
|
|
|
while (rxr_count) {
|
|
/* assign generic ring traits */
|
|
ring->dev = &adapter->pdev->dev;
|
|
ring->netdev = adapter->netdev;
|
|
|
|
/* configure backlink on ring */
|
|
ring->q_vector = q_vector;
|
|
|
|
/* update q_vector Rx values */
|
|
ixgbe_add_ring(ring, &q_vector->rx);
|
|
|
|
/*
|
|
* 82599 errata, UDP frames with a 0 checksum
|
|
* can be marked as checksum errors.
|
|
*/
|
|
if (adapter->hw.mac.type == ixgbe_mac_82599EB)
|
|
set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state);
|
|
|
|
#ifdef IXGBE_FCOE
|
|
if (adapter->netdev->features & NETIF_F_FCOE_MTU) {
|
|
struct ixgbe_ring_feature *f;
|
|
f = &adapter->ring_feature[RING_F_FCOE];
|
|
if ((rxr_idx >= f->offset) &&
|
|
(rxr_idx < f->offset + f->indices))
|
|
set_bit(__IXGBE_RX_FCOE, &ring->state);
|
|
}
|
|
|
|
#endif /* IXGBE_FCOE */
|
|
/* apply Rx specific ring traits */
|
|
ring->count = adapter->rx_ring_count;
|
|
ring->queue_index = rxr_idx;
|
|
|
|
/* assign ring to adapter */
|
|
adapter->rx_ring[rxr_idx] = ring;
|
|
|
|
/* update count and index */
|
|
rxr_count--;
|
|
rxr_idx += v_count;
|
|
|
|
/* push pointer to next ring */
|
|
ring++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_free_q_vector - Free memory allocated for specific interrupt vector
|
|
* @adapter: board private structure to initialize
|
|
* @v_idx: Index of vector to be freed
|
|
*
|
|
* This function frees the memory allocated to the q_vector. In addition if
|
|
* NAPI is enabled it will delete any references to the NAPI struct prior
|
|
* to freeing the q_vector.
|
|
**/
|
|
static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx)
|
|
{
|
|
struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
|
|
struct ixgbe_ring *ring;
|
|
|
|
ixgbe_for_each_ring(ring, q_vector->tx)
|
|
adapter->tx_ring[ring->queue_index] = NULL;
|
|
|
|
ixgbe_for_each_ring(ring, q_vector->rx)
|
|
adapter->rx_ring[ring->queue_index] = NULL;
|
|
|
|
adapter->q_vector[v_idx] = NULL;
|
|
netif_napi_del(&q_vector->napi);
|
|
|
|
/*
|
|
* ixgbe_get_stats64() might access the rings on this vector,
|
|
* we must wait a grace period before freeing it.
|
|
*/
|
|
kfree_rcu(q_vector, rcu);
|
|
}
|
|
|
|
/**
|
|
* ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
|
|
* @adapter: board private structure to initialize
|
|
*
|
|
* We allocate one q_vector per queue interrupt. If allocation fails we
|
|
* return -ENOMEM.
|
|
**/
|
|
static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
|
|
{
|
|
int q_vectors = adapter->num_q_vectors;
|
|
int rxr_remaining = adapter->num_rx_queues;
|
|
int txr_remaining = adapter->num_tx_queues;
|
|
int rxr_idx = 0, txr_idx = 0, v_idx = 0;
|
|
int err;
|
|
|
|
/* only one q_vector if MSI-X is disabled. */
|
|
if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
|
|
q_vectors = 1;
|
|
|
|
if (q_vectors >= (rxr_remaining + txr_remaining)) {
|
|
for (; rxr_remaining; v_idx++) {
|
|
err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx,
|
|
0, 0, 1, rxr_idx);
|
|
|
|
if (err)
|
|
goto err_out;
|
|
|
|
/* update counts and index */
|
|
rxr_remaining--;
|
|
rxr_idx++;
|
|
}
|
|
}
|
|
|
|
for (; v_idx < q_vectors; v_idx++) {
|
|
int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
|
|
int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
|
|
err = ixgbe_alloc_q_vector(adapter, q_vectors, v_idx,
|
|
tqpv, txr_idx,
|
|
rqpv, rxr_idx);
|
|
|
|
if (err)
|
|
goto err_out;
|
|
|
|
/* update counts and index */
|
|
rxr_remaining -= rqpv;
|
|
txr_remaining -= tqpv;
|
|
rxr_idx++;
|
|
txr_idx++;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
adapter->num_tx_queues = 0;
|
|
adapter->num_rx_queues = 0;
|
|
adapter->num_q_vectors = 0;
|
|
|
|
while (v_idx--)
|
|
ixgbe_free_q_vector(adapter, v_idx);
|
|
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
|
|
* @adapter: board private structure to initialize
|
|
*
|
|
* This function frees the memory allocated to the q_vectors. In addition if
|
|
* NAPI is enabled it will delete any references to the NAPI struct prior
|
|
* to freeing the q_vector.
|
|
**/
|
|
static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
|
|
{
|
|
int v_idx = adapter->num_q_vectors;
|
|
|
|
adapter->num_tx_queues = 0;
|
|
adapter->num_rx_queues = 0;
|
|
adapter->num_q_vectors = 0;
|
|
|
|
while (v_idx--)
|
|
ixgbe_free_q_vector(adapter, v_idx);
|
|
}
|
|
|
|
static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
|
|
{
|
|
if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
|
|
adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
|
|
pci_disable_msix(adapter->pdev);
|
|
kfree(adapter->msix_entries);
|
|
adapter->msix_entries = NULL;
|
|
} else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
|
|
adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
|
|
pci_disable_msi(adapter->pdev);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
|
|
* @adapter: board private structure to initialize
|
|
*
|
|
* Attempt to configure the interrupts using the best available
|
|
* capabilities of the hardware and the kernel.
|
|
**/
|
|
static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
|
|
{
|
|
struct ixgbe_hw *hw = &adapter->hw;
|
|
int err = 0;
|
|
int vector, v_budget;
|
|
|
|
/*
|
|
* It's easy to be greedy for MSI-X vectors, but it really
|
|
* doesn't do us much good if we have a lot more vectors
|
|
* than CPU's. So let's be conservative and only ask for
|
|
* (roughly) the same number of vectors as there are CPU's.
|
|
* The default is to use pairs of vectors.
|
|
*/
|
|
v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues);
|
|
v_budget = min_t(int, v_budget, num_online_cpus());
|
|
v_budget += NON_Q_VECTORS;
|
|
|
|
/*
|
|
* At the same time, hardware can only support a maximum of
|
|
* hw.mac->max_msix_vectors vectors. With features
|
|
* such as RSS and VMDq, we can easily surpass the number of Rx and Tx
|
|
* descriptor queues supported by our device. Thus, we cap it off in
|
|
* those rare cases where the cpu count also exceeds our vector limit.
|
|
*/
|
|
v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors);
|
|
|
|
/* A failure in MSI-X entry allocation isn't fatal, but it does
|
|
* mean we disable MSI-X capabilities of the adapter. */
|
|
adapter->msix_entries = kcalloc(v_budget,
|
|
sizeof(struct msix_entry), GFP_KERNEL);
|
|
if (adapter->msix_entries) {
|
|
for (vector = 0; vector < v_budget; vector++)
|
|
adapter->msix_entries[vector].entry = vector;
|
|
|
|
ixgbe_acquire_msix_vectors(adapter, v_budget);
|
|
|
|
if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
|
|
goto out;
|
|
}
|
|
|
|
adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
|
|
adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
|
|
if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
|
|
e_err(probe,
|
|
"ATR is not supported while multiple "
|
|
"queues are disabled. Disabling Flow Director\n");
|
|
}
|
|
adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
|
|
adapter->atr_sample_rate = 0;
|
|
if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
|
|
ixgbe_disable_sriov(adapter);
|
|
|
|
err = ixgbe_set_num_queues(adapter);
|
|
if (err)
|
|
return err;
|
|
|
|
adapter->num_q_vectors = 1;
|
|
|
|
err = pci_enable_msi(adapter->pdev);
|
|
if (!err) {
|
|
adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
|
|
} else {
|
|
netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
|
|
"Unable to allocate MSI interrupt, "
|
|
"falling back to legacy. Error: %d\n", err);
|
|
/* reset err */
|
|
err = 0;
|
|
}
|
|
|
|
out:
|
|
return err;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
|
|
* @adapter: board private structure to initialize
|
|
*
|
|
* We determine which interrupt scheme to use based on...
|
|
* - Kernel support (MSI, MSI-X)
|
|
* - which can be user-defined (via MODULE_PARAM)
|
|
* - Hardware queue count (num_*_queues)
|
|
* - defined by miscellaneous hardware support/features (RSS, etc.)
|
|
**/
|
|
int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
|
|
{
|
|
int err;
|
|
|
|
/* Number of supported queues */
|
|
err = ixgbe_set_num_queues(adapter);
|
|
if (err)
|
|
return err;
|
|
|
|
err = ixgbe_set_interrupt_capability(adapter);
|
|
if (err) {
|
|
e_dev_err("Unable to setup interrupt capabilities\n");
|
|
goto err_set_interrupt;
|
|
}
|
|
|
|
err = ixgbe_alloc_q_vectors(adapter);
|
|
if (err) {
|
|
e_dev_err("Unable to allocate memory for queue vectors\n");
|
|
goto err_alloc_q_vectors;
|
|
}
|
|
|
|
ixgbe_cache_ring_register(adapter);
|
|
|
|
e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
|
|
(adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
|
|
adapter->num_rx_queues, adapter->num_tx_queues);
|
|
|
|
set_bit(__IXGBE_DOWN, &adapter->state);
|
|
|
|
return 0;
|
|
|
|
err_alloc_q_vectors:
|
|
ixgbe_reset_interrupt_capability(adapter);
|
|
err_set_interrupt:
|
|
return err;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
|
|
* @adapter: board private structure to clear interrupt scheme on
|
|
*
|
|
* We go through and clear interrupt specific resources and reset the structure
|
|
* to pre-load conditions
|
|
**/
|
|
void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
|
|
{
|
|
adapter->num_tx_queues = 0;
|
|
adapter->num_rx_queues = 0;
|
|
|
|
ixgbe_free_q_vectors(adapter);
|
|
ixgbe_reset_interrupt_capability(adapter);
|
|
}
|
|
|
|
void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
|
|
u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
|
|
{
|
|
struct ixgbe_adv_tx_context_desc *context_desc;
|
|
u16 i = tx_ring->next_to_use;
|
|
|
|
context_desc = IXGBE_TX_CTXTDESC(tx_ring, i);
|
|
|
|
i++;
|
|
tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
|
|
|
|
/* set bits to identify this as an advanced context descriptor */
|
|
type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
|
|
|
|
context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
|
|
context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
|
|
context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
|
|
context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
|
|
}
|
|
|