Grygorii Strashko 6af0a549c2 ARM: dts: dra7: fix cpsw mdio fck clock ... The DRA7 CPSW MDIO functional clock (gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0) is specified incorrectly, which is caused incorrect MDIO bus clock configuration MDCLK. The correct CPSW MDIO functional clock is gmac_main_clk (125MHz), which is the same as CPSW fck. Hence fix it. Fixes: 1faa415c9c ("ARM: dts: Add fck for cpsw mdio for omap variants") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>		2019-11-20 09:42:33 -08:00
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dts	ARM: dts: dra7: fix cpsw mdio fck clock	2019-11-20 09:42:33 -08:00
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