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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5bc9900add
On some Qualcomm SoCs, Operating State Manager (OSM) controls the resources of scaling L3 caches. Add a driver to handle bandwidth requests to OSM L3 from CPU on SDM845 SoCs. Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Evan Green <evgreen@chromium.org> Link: https://lore.kernel.org/r/20200227105632.15041-4-sibis@codeaurora.org Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
143 lines
5.1 KiB
C
143 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
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#define __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
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#define SDM845_MASTER_A1NOC_CFG 1
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#define SDM845_MASTER_BLSP_1 2
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#define SDM845_MASTER_TSIF 3
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#define SDM845_MASTER_SDCC_2 4
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#define SDM845_MASTER_SDCC_4 5
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#define SDM845_MASTER_UFS_CARD 6
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#define SDM845_MASTER_UFS_MEM 7
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#define SDM845_MASTER_PCIE_0 8
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#define SDM845_MASTER_A2NOC_CFG 9
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#define SDM845_MASTER_QDSS_BAM 10
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#define SDM845_MASTER_BLSP_2 11
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#define SDM845_MASTER_CNOC_A2NOC 12
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#define SDM845_MASTER_CRYPTO 13
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#define SDM845_MASTER_IPA 14
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#define SDM845_MASTER_PCIE_1 15
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#define SDM845_MASTER_QDSS_ETR 16
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#define SDM845_MASTER_USB3_0 17
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#define SDM845_MASTER_USB3_1 18
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#define SDM845_MASTER_CAMNOC_HF0_UNCOMP 19
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#define SDM845_MASTER_CAMNOC_HF1_UNCOMP 20
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#define SDM845_MASTER_CAMNOC_SF_UNCOMP 21
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#define SDM845_MASTER_SPDM 22
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#define SDM845_MASTER_TIC 23
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#define SDM845_MASTER_SNOC_CNOC 24
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#define SDM845_MASTER_QDSS_DAP 25
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#define SDM845_MASTER_CNOC_DC_NOC 26
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#define SDM845_MASTER_APPSS_PROC 27
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#define SDM845_MASTER_GNOC_CFG 28
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#define SDM845_MASTER_LLCC 29
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#define SDM845_MASTER_TCU_0 30
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#define SDM845_MASTER_MEM_NOC_CFG 31
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#define SDM845_MASTER_GNOC_MEM_NOC 32
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#define SDM845_MASTER_MNOC_HF_MEM_NOC 33
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#define SDM845_MASTER_MNOC_SF_MEM_NOC 34
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#define SDM845_MASTER_SNOC_GC_MEM_NOC 35
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#define SDM845_MASTER_SNOC_SF_MEM_NOC 36
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#define SDM845_MASTER_GFX3D 37
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#define SDM845_MASTER_CNOC_MNOC_CFG 38
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#define SDM845_MASTER_CAMNOC_HF0 39
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#define SDM845_MASTER_CAMNOC_HF1 40
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#define SDM845_MASTER_CAMNOC_SF 41
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#define SDM845_MASTER_MDP0 42
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#define SDM845_MASTER_MDP1 43
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#define SDM845_MASTER_ROTATOR 44
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#define SDM845_MASTER_VIDEO_P0 45
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#define SDM845_MASTER_VIDEO_P1 46
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#define SDM845_MASTER_VIDEO_PROC 47
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#define SDM845_MASTER_SNOC_CFG 48
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#define SDM845_MASTER_A1NOC_SNOC 49
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#define SDM845_MASTER_A2NOC_SNOC 50
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#define SDM845_MASTER_GNOC_SNOC 51
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#define SDM845_MASTER_MEM_NOC_SNOC 52
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#define SDM845_MASTER_ANOC_PCIE_SNOC 53
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#define SDM845_MASTER_PIMEM 54
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#define SDM845_MASTER_GIC 55
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#define SDM845_SLAVE_A1NOC_SNOC 56
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#define SDM845_SLAVE_SERVICE_A1NOC 57
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#define SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC 58
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#define SDM845_SLAVE_A2NOC_SNOC 59
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#define SDM845_SLAVE_ANOC_PCIE_SNOC 60
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#define SDM845_SLAVE_SERVICE_A2NOC 61
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#define SDM845_SLAVE_CAMNOC_UNCOMP 62
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#define SDM845_SLAVE_A1NOC_CFG 63
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#define SDM845_SLAVE_A2NOC_CFG 64
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#define SDM845_SLAVE_AOP 65
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#define SDM845_SLAVE_AOSS 66
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#define SDM845_SLAVE_CAMERA_CFG 67
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#define SDM845_SLAVE_CLK_CTL 68
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#define SDM845_SLAVE_CDSP_CFG 69
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#define SDM845_SLAVE_RBCPR_CX_CFG 70
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#define SDM845_SLAVE_CRYPTO_0_CFG 71
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#define SDM845_SLAVE_DCC_CFG 72
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#define SDM845_SLAVE_CNOC_DDRSS 73
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#define SDM845_SLAVE_DISPLAY_CFG 74
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#define SDM845_SLAVE_GLM 75
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#define SDM845_SLAVE_GFX3D_CFG 76
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#define SDM845_SLAVE_IMEM_CFG 77
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#define SDM845_SLAVE_IPA_CFG 78
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#define SDM845_SLAVE_CNOC_MNOC_CFG 79
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#define SDM845_SLAVE_PCIE_0_CFG 80
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#define SDM845_SLAVE_PCIE_1_CFG 81
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#define SDM845_SLAVE_PDM 82
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#define SDM845_SLAVE_SOUTH_PHY_CFG 83
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#define SDM845_SLAVE_PIMEM_CFG 84
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#define SDM845_SLAVE_PRNG 85
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#define SDM845_SLAVE_QDSS_CFG 86
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#define SDM845_SLAVE_BLSP_2 87
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#define SDM845_SLAVE_BLSP_1 88
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#define SDM845_SLAVE_SDCC_2 89
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#define SDM845_SLAVE_SDCC_4 90
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#define SDM845_SLAVE_SNOC_CFG 91
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#define SDM845_SLAVE_SPDM_WRAPPER 92
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#define SDM845_SLAVE_SPSS_CFG 93
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#define SDM845_SLAVE_TCSR 94
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#define SDM845_SLAVE_TLMM_NORTH 95
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#define SDM845_SLAVE_TLMM_SOUTH 96
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#define SDM845_SLAVE_TSIF 97
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#define SDM845_SLAVE_UFS_CARD_CFG 98
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#define SDM845_SLAVE_UFS_MEM_CFG 99
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#define SDM845_SLAVE_USB3_0 100
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#define SDM845_SLAVE_USB3_1 101
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#define SDM845_SLAVE_VENUS_CFG 102
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#define SDM845_SLAVE_VSENSE_CTRL_CFG 103
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#define SDM845_SLAVE_CNOC_A2NOC 104
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#define SDM845_SLAVE_SERVICE_CNOC 105
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#define SDM845_SLAVE_LLCC_CFG 106
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#define SDM845_SLAVE_MEM_NOC_CFG 107
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#define SDM845_SLAVE_GNOC_SNOC 108
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#define SDM845_SLAVE_GNOC_MEM_NOC 109
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#define SDM845_SLAVE_SERVICE_GNOC 110
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#define SDM845_SLAVE_EBI1 111
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#define SDM845_SLAVE_MSS_PROC_MS_MPU_CFG 112
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#define SDM845_SLAVE_MEM_NOC_GNOC 113
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#define SDM845_SLAVE_LLCC 114
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#define SDM845_SLAVE_MEM_NOC_SNOC 115
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#define SDM845_SLAVE_SERVICE_MEM_NOC 116
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#define SDM845_SLAVE_MNOC_SF_MEM_NOC 117
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#define SDM845_SLAVE_MNOC_HF_MEM_NOC 118
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#define SDM845_SLAVE_SERVICE_MNOC 119
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#define SDM845_SLAVE_APPSS 120
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#define SDM845_SLAVE_SNOC_CNOC 121
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#define SDM845_SLAVE_SNOC_MEM_NOC_GC 122
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#define SDM845_SLAVE_SNOC_MEM_NOC_SF 123
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#define SDM845_SLAVE_IMEM 124
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#define SDM845_SLAVE_PCIE_0 125
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#define SDM845_SLAVE_PCIE_1 126
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#define SDM845_SLAVE_PIMEM 127
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#define SDM845_SLAVE_SERVICE_SNOC 128
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#define SDM845_SLAVE_QDSS_STM 129
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#define SDM845_SLAVE_TCU 130
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#define SDM845_MASTER_OSM_L3_APPS 131
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#define SDM845_SLAVE_OSM_L3 132
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#endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */
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