mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 06:59:28 +07:00
943682e3bd
The Jasper Lake PCH follows ICP/TGP's south display behavior and is identical to MCC graphics-wise except that it does not use the unusual (port C -> TC1) pin mapping that MCC does. Also, it turns out the extra PCH ID that we had previously thought was a form of MCC is actually a second ID for JSP (i.e., port C uses the port C pins instead of the TC1 pins). v2: - Also update the port masks (not just the pin table) in mcc_hpd_irq_setup. (Vivek) v3: - Break jsp_hpd_irq_setup out into its own function for clarity. (Vivek) Cc: José Roberto de Souza <jose.souza@intel.com> Cc: James Ausmus <james.ausmus@intel.com> Cc: Vivek Kasireddy <vivek.kasireddy@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Vivek Kasireddy <vivek.kasireddy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191015162854.30546-1-matthew.d.roper@intel.com
78 lines
3.1 KiB
C
78 lines
3.1 KiB
C
/* SPDX-License-Identifier: MIT */
|
|
/*
|
|
* Copyright 2019 Intel Corporation.
|
|
*/
|
|
|
|
#ifndef __INTEL_PCH__
|
|
#define __INTEL_PCH__
|
|
|
|
struct drm_i915_private;
|
|
|
|
/*
|
|
* Sorted by south display engine compatibility.
|
|
* If the new PCH comes with a south display engine that is not
|
|
* inherited from the latest item, please do not add it to the
|
|
* end. Instead, add it right after its "parent" PCH.
|
|
*/
|
|
enum intel_pch {
|
|
PCH_NOP = -1, /* PCH without south display */
|
|
PCH_NONE = 0, /* No PCH present */
|
|
PCH_IBX, /* Ibexpeak PCH */
|
|
PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
|
|
PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
|
|
PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
|
|
PCH_CNP, /* Cannon/Comet Lake PCH */
|
|
PCH_ICP, /* Ice Lake PCH */
|
|
PCH_JSP, /* Jasper Lake PCH */
|
|
PCH_MCC, /* Mule Creek Canyon PCH */
|
|
PCH_TGP, /* Tiger Lake PCH */
|
|
};
|
|
|
|
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
|
|
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
|
|
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
|
|
#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
|
|
#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
|
|
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
|
|
#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
|
|
#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
|
|
#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
|
|
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
|
|
#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
|
|
#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
|
|
#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
|
|
#define INTEL_PCH_CMP_DEVICE_ID_TYPE 0x0280
|
|
#define INTEL_PCH_CMP2_DEVICE_ID_TYPE 0x0680
|
|
#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
|
|
#define INTEL_PCH_MCC_DEVICE_ID_TYPE 0x4B00
|
|
#define INTEL_PCH_TGP_DEVICE_ID_TYPE 0xA080
|
|
#define INTEL_PCH_JSP_DEVICE_ID_TYPE 0x4D80
|
|
#define INTEL_PCH_JSP2_DEVICE_ID_TYPE 0x3880
|
|
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
|
|
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
|
|
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
|
|
|
|
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
|
|
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
|
|
#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
|
|
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
|
|
#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
|
|
#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
|
|
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
|
|
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
|
|
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
|
|
#define HAS_PCH_LPT_LP(dev_priv) \
|
|
(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
|
|
INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
|
|
#define HAS_PCH_LPT_H(dev_priv) \
|
|
(INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
|
|
INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
|
|
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
|
|
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
|
|
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
|
|
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
|
|
|
|
void intel_detect_pch(struct drm_i915_private *dev_priv);
|
|
|
|
#endif /* __INTEL_PCH__ */
|