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6a0e20cd8c
New features: - SECCOMP support - nommu support - SBI-less system support - M-Mode support - TLB flush optimizations Other improvements: - Pass the complete RISC-V ISA string supported by the CPU cores to userspace, rather than redacting parts of it in the kernel - Add platform DMA IP block data to the HiFive Unleashed board DT file - Add Makefile support for BZ2, LZ4, LZMA, LZO kernel image compression formats, in line with other architectures Cleanups: - Remove unnecessary PTE_PARENT_SIZE macro - Standardize include guard naming across arch/riscv -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEElRDoIDdEz9/svf2Kx4+xDQu9KksFAl3dkMcACgkQx4+xDQu9 KksoQA/+MZdtMrSe+j5yep7ZO803ivdS5tPCjNI06An2Ps8OJmJKoU8zSCIbygfM xIQ8R5KVLjd1DTW3SKNrL3bUsH0PdwGHKj69z0gMA01kGBe5CfJEzHw03U4It++t xaPAYJje99xtdEzZMro/Z+/Gsz/XM5SDZmY4i6quSlHOmL0HP6zftk3jPvxO+XtD 7unQJSHuZElqs984OmR+6DUTiaIlJ4P+/xxlFydswq19/tDNCXpukLhMHkOND3W+ 3dBHAp9U18dz2I8lD3xlppVbvgCnud7z+xa+XY1Q/BluoYIEe6714S+9lr8TCdTP 43wL9hSvbDPyaydnmKU7VqwdcWrbVQkA7H3GtxeiUZYvyDdidk9sARqg0n6uoedw 48uRfeI0jCQXh6XdFNMCqNgYPpcpHY3isMKVCi2U6TT0fNdUUC3f62qsOIP0vQXh 4hDys5JzIoBKv8nz/ap+1xzUluBt6FGmySPlTbd8ryn2m2Yd0EsHjywcEGRJMrlM KcOYgLAKcr9rRF4ap/NqQy74AvC+pOcDVeUHPD0WXYDRQn6L0wbp8YElzRf8W1BC b7osrRSNLfzC2LsEUEK+qYHrT4+cuWBbkuobAEHMY/OnLW1OKEifZQIdknAE1/yg n2qy4DuA6qta+Q1GiH8OOt9AEYHPw+SDP3+qFaJK5ZZMb3v565A= =nbwY -----END PGP SIGNATURE----- Merge tag 'riscv/for-v5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Paul Walmsley: "New features: - SECCOMP support - nommu support - SBI-less system support - M-Mode support - TLB flush optimizations Other improvements: - Pass the complete RISC-V ISA string supported by the CPU cores to userspace, rather than redacting parts of it in the kernel - Add platform DMA IP block data to the HiFive Unleashed board DT file - Add Makefile support for BZ2, LZ4, LZMA, LZO kernel image compression formats, in line with other architectures Cleanups: - Remove unnecessary PTE_PARENT_SIZE macro - Standardize include guard naming across arch/riscv" * tag 'riscv/for-v5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (22 commits) riscv: provide a flat image loader riscv: add nommu support riscv: clear the instruction cache and all registers when booting riscv: read the hart ID from mhartid on boot riscv: provide native clint access for M-mode riscv: dts: add support for PDMA device of HiFive Unleashed Rev A00 riscv: add support for MMIO access to the timer registers riscv: implement remote sfence.i using IPIs riscv: cleanup the default power off implementation riscv: poison SBI calls for M-mode riscv: don't allow selecting SBI based drivers for M-mode RISC-V: Add multiple compression image format. riscv: clean up the macro format in each header file riscv: Use PMD_SIZE to replace PTE_PARENT_SIZE riscv: abstract out CSR names for supervisor vs machine mode riscv: separate MMIO functions into their own header file riscv: enter WFI in default_power_off() if SBI does not shutdown RISC-V: Issue a tlb page flush if possible RISC-V: Issue a local tlbflush if possible. RISC-V: Do not invoke SBI call if cpumask is empty ... |
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Makefile |