mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 20:26:48 +07:00
bdb85cd1d2
Now that we have switched to the small code model entirely, and reduced the extended KASLR range to 4 GB, we can be sure that the targets of relative branches that are out of range are in range for a ADRP/ADD pair, which is one instruction shorter than our current MOVN/MOVK/MOVK sequence, and is more idiomatic and so it is more likely to be implemented efficiently by micro-architectures. So switch over the ordinary PLT code and the special handling of the Cortex-A53 ADRP errata, as well as the ftrace trampline handling. Reviewed-by: Torsten Duwe <duwe@lst.de> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> [will: Added a couple of comments in the plt equality check] Signed-off-by: Will Deacon <will.deacon@arm.com>
461 lines
12 KiB
C
461 lines
12 KiB
C
/*
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* AArch64 loadable module support.
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*
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* Copyright (C) 2012 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*/
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#include <linux/bitops.h>
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#include <linux/elf.h>
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#include <linux/gfp.h>
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#include <linux/kasan.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/moduleloader.h>
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#include <linux/vmalloc.h>
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#include <asm/alternative.h>
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#include <asm/insn.h>
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#include <asm/sections.h>
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void *module_alloc(unsigned long size)
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{
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gfp_t gfp_mask = GFP_KERNEL;
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void *p;
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/* Silence the initial allocation */
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if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS))
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gfp_mask |= __GFP_NOWARN;
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p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
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module_alloc_base + MODULES_VSIZE,
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gfp_mask, PAGE_KERNEL_EXEC, 0,
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NUMA_NO_NODE, __builtin_return_address(0));
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if (!p && IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
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!IS_ENABLED(CONFIG_KASAN))
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/*
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* KASAN can only deal with module allocations being served
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* from the reserved module region, since the remainder of
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* the vmalloc region is already backed by zero shadow pages,
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* and punching holes into it is non-trivial. Since the module
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* region is not randomized when KASAN is enabled, it is even
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* less likely that the module region gets exhausted, so we
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* can simply omit this fallback in that case.
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*/
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p = __vmalloc_node_range(size, MODULE_ALIGN, module_alloc_base,
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module_alloc_base + SZ_4G, GFP_KERNEL,
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PAGE_KERNEL_EXEC, 0, NUMA_NO_NODE,
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__builtin_return_address(0));
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if (p && (kasan_module_alloc(p, size) < 0)) {
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vfree(p);
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return NULL;
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}
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return p;
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}
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enum aarch64_reloc_op {
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RELOC_OP_NONE,
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RELOC_OP_ABS,
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RELOC_OP_PREL,
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RELOC_OP_PAGE,
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};
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static u64 do_reloc(enum aarch64_reloc_op reloc_op, __le32 *place, u64 val)
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{
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switch (reloc_op) {
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case RELOC_OP_ABS:
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return val;
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case RELOC_OP_PREL:
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return val - (u64)place;
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case RELOC_OP_PAGE:
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return (val & ~0xfff) - ((u64)place & ~0xfff);
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case RELOC_OP_NONE:
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return 0;
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}
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pr_err("do_reloc: unknown relocation operation %d\n", reloc_op);
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return 0;
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}
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static int reloc_data(enum aarch64_reloc_op op, void *place, u64 val, int len)
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{
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s64 sval = do_reloc(op, place, val);
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switch (len) {
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case 16:
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*(s16 *)place = sval;
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if (sval < S16_MIN || sval > U16_MAX)
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return -ERANGE;
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break;
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case 32:
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*(s32 *)place = sval;
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if (sval < S32_MIN || sval > U32_MAX)
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return -ERANGE;
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break;
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case 64:
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*(s64 *)place = sval;
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break;
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default:
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pr_err("Invalid length (%d) for data relocation\n", len);
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return 0;
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}
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return 0;
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}
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enum aarch64_insn_movw_imm_type {
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AARCH64_INSN_IMM_MOVNZ,
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AARCH64_INSN_IMM_MOVKZ,
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};
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static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u64 val,
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int lsb, enum aarch64_insn_movw_imm_type imm_type)
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{
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u64 imm;
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s64 sval;
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u32 insn = le32_to_cpu(*place);
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sval = do_reloc(op, place, val);
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imm = sval >> lsb;
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if (imm_type == AARCH64_INSN_IMM_MOVNZ) {
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/*
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* For signed MOVW relocations, we have to manipulate the
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* instruction encoding depending on whether or not the
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* immediate is less than zero.
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*/
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insn &= ~(3 << 29);
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if (sval >= 0) {
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/* >=0: Set the instruction to MOVZ (opcode 10b). */
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insn |= 2 << 29;
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} else {
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/*
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* <0: Set the instruction to MOVN (opcode 00b).
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* Since we've masked the opcode already, we
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* don't need to do anything other than
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* inverting the new immediate field.
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*/
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imm = ~imm;
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}
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}
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/* Update the instruction with the new encoding. */
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insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm);
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*place = cpu_to_le32(insn);
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if (imm > U16_MAX)
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return -ERANGE;
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return 0;
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}
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static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64 val,
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int lsb, int len, enum aarch64_insn_imm_type imm_type)
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{
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u64 imm, imm_mask;
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s64 sval;
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u32 insn = le32_to_cpu(*place);
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/* Calculate the relocation value. */
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sval = do_reloc(op, place, val);
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sval >>= lsb;
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/* Extract the value bits and shift them to bit 0. */
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imm_mask = (BIT(lsb + len) - 1) >> lsb;
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imm = sval & imm_mask;
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/* Update the instruction's immediate field. */
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insn = aarch64_insn_encode_immediate(imm_type, insn, imm);
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*place = cpu_to_le32(insn);
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/*
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* Extract the upper value bits (including the sign bit) and
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* shift them to bit 0.
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*/
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sval = (s64)(sval & ~(imm_mask >> 1)) >> (len - 1);
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/*
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* Overflow has occurred if the upper bits are not all equal to
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* the sign bit of the value.
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*/
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if ((u64)(sval + 1) >= 2)
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return -ERANGE;
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return 0;
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}
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static int reloc_insn_adrp(struct module *mod, Elf64_Shdr *sechdrs,
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__le32 *place, u64 val)
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{
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u32 insn;
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if (!is_forbidden_offset_for_adrp(place))
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return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
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AARCH64_INSN_IMM_ADR);
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/* patch ADRP to ADR if it is in range */
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if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21,
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AARCH64_INSN_IMM_ADR)) {
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insn = le32_to_cpu(*place);
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insn &= ~BIT(31);
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} else {
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/* out of range for ADR -> emit a veneer */
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val = module_emit_veneer_for_adrp(mod, sechdrs, place, val & ~0xfff);
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if (!val)
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return -ENOEXEC;
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insn = aarch64_insn_gen_branch_imm((u64)place, val,
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AARCH64_INSN_BRANCH_NOLINK);
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}
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*place = cpu_to_le32(insn);
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return 0;
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}
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int apply_relocate_add(Elf64_Shdr *sechdrs,
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const char *strtab,
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unsigned int symindex,
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unsigned int relsec,
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struct module *me)
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{
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unsigned int i;
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int ovf;
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bool overflow_check;
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Elf64_Sym *sym;
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void *loc;
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u64 val;
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Elf64_Rela *rel = (void *)sechdrs[relsec].sh_addr;
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for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
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/* loc corresponds to P in the AArch64 ELF document. */
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loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
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+ rel[i].r_offset;
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/* sym is the ELF symbol we're referring to. */
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sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
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+ ELF64_R_SYM(rel[i].r_info);
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/* val corresponds to (S + A) in the AArch64 ELF document. */
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val = sym->st_value + rel[i].r_addend;
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/* Check for overflow by default. */
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overflow_check = true;
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/* Perform the static relocation. */
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switch (ELF64_R_TYPE(rel[i].r_info)) {
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/* Null relocations. */
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case R_ARM_NONE:
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case R_AARCH64_NONE:
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ovf = 0;
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break;
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/* Data relocations. */
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case R_AARCH64_ABS64:
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overflow_check = false;
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ovf = reloc_data(RELOC_OP_ABS, loc, val, 64);
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break;
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case R_AARCH64_ABS32:
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ovf = reloc_data(RELOC_OP_ABS, loc, val, 32);
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break;
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case R_AARCH64_ABS16:
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ovf = reloc_data(RELOC_OP_ABS, loc, val, 16);
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break;
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case R_AARCH64_PREL64:
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overflow_check = false;
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ovf = reloc_data(RELOC_OP_PREL, loc, val, 64);
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break;
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case R_AARCH64_PREL32:
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ovf = reloc_data(RELOC_OP_PREL, loc, val, 32);
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break;
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case R_AARCH64_PREL16:
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ovf = reloc_data(RELOC_OP_PREL, loc, val, 16);
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break;
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/* MOVW instruction relocations. */
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case R_AARCH64_MOVW_UABS_G0_NC:
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overflow_check = false;
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case R_AARCH64_MOVW_UABS_G0:
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ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
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AARCH64_INSN_IMM_MOVKZ);
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break;
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case R_AARCH64_MOVW_UABS_G1_NC:
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overflow_check = false;
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case R_AARCH64_MOVW_UABS_G1:
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ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
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AARCH64_INSN_IMM_MOVKZ);
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break;
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case R_AARCH64_MOVW_UABS_G2_NC:
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overflow_check = false;
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case R_AARCH64_MOVW_UABS_G2:
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ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
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AARCH64_INSN_IMM_MOVKZ);
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break;
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case R_AARCH64_MOVW_UABS_G3:
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/* We're using the top bits so we can't overflow. */
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overflow_check = false;
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ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,
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AARCH64_INSN_IMM_MOVKZ);
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break;
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case R_AARCH64_MOVW_SABS_G0:
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ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,
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AARCH64_INSN_IMM_MOVNZ);
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break;
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case R_AARCH64_MOVW_SABS_G1:
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ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,
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AARCH64_INSN_IMM_MOVNZ);
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break;
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case R_AARCH64_MOVW_SABS_G2:
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ovf = reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,
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AARCH64_INSN_IMM_MOVNZ);
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break;
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case R_AARCH64_MOVW_PREL_G0_NC:
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overflow_check = false;
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ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
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AARCH64_INSN_IMM_MOVKZ);
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break;
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case R_AARCH64_MOVW_PREL_G0:
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ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,
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AARCH64_INSN_IMM_MOVNZ);
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break;
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case R_AARCH64_MOVW_PREL_G1_NC:
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overflow_check = false;
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ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
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AARCH64_INSN_IMM_MOVKZ);
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break;
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case R_AARCH64_MOVW_PREL_G1:
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ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,
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AARCH64_INSN_IMM_MOVNZ);
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break;
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case R_AARCH64_MOVW_PREL_G2_NC:
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overflow_check = false;
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ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
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AARCH64_INSN_IMM_MOVKZ);
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break;
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case R_AARCH64_MOVW_PREL_G2:
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ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,
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AARCH64_INSN_IMM_MOVNZ);
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break;
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case R_AARCH64_MOVW_PREL_G3:
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/* We're using the top bits so we can't overflow. */
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overflow_check = false;
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ovf = reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,
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AARCH64_INSN_IMM_MOVNZ);
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break;
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/* Immediate instruction relocations. */
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case R_AARCH64_LD_PREL_LO19:
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ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
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AARCH64_INSN_IMM_19);
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break;
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case R_AARCH64_ADR_PREL_LO21:
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ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,
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AARCH64_INSN_IMM_ADR);
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break;
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case R_AARCH64_ADR_PREL_PG_HI21_NC:
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overflow_check = false;
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case R_AARCH64_ADR_PREL_PG_HI21:
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ovf = reloc_insn_adrp(me, sechdrs, loc, val);
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if (ovf && ovf != -ERANGE)
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return ovf;
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break;
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case R_AARCH64_ADD_ABS_LO12_NC:
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case R_AARCH64_LDST8_ABS_LO12_NC:
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overflow_check = false;
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ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,
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AARCH64_INSN_IMM_12);
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break;
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case R_AARCH64_LDST16_ABS_LO12_NC:
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overflow_check = false;
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ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,
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AARCH64_INSN_IMM_12);
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break;
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case R_AARCH64_LDST32_ABS_LO12_NC:
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overflow_check = false;
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ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,
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AARCH64_INSN_IMM_12);
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break;
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case R_AARCH64_LDST64_ABS_LO12_NC:
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overflow_check = false;
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ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,
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AARCH64_INSN_IMM_12);
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break;
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case R_AARCH64_LDST128_ABS_LO12_NC:
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overflow_check = false;
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ovf = reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,
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AARCH64_INSN_IMM_12);
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break;
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case R_AARCH64_TSTBR14:
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ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,
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AARCH64_INSN_IMM_14);
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break;
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case R_AARCH64_CONDBR19:
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ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,
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AARCH64_INSN_IMM_19);
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break;
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case R_AARCH64_JUMP26:
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case R_AARCH64_CALL26:
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ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,
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AARCH64_INSN_IMM_26);
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if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&
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ovf == -ERANGE) {
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val = module_emit_plt_entry(me, sechdrs, loc, &rel[i], sym);
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if (!val)
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return -ENOEXEC;
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ovf = reloc_insn_imm(RELOC_OP_PREL, loc, val, 2,
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26, AARCH64_INSN_IMM_26);
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}
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break;
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default:
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pr_err("module %s: unsupported RELA relocation: %llu\n",
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me->name, ELF64_R_TYPE(rel[i].r_info));
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return -ENOEXEC;
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}
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if (overflow_check && ovf == -ERANGE)
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goto overflow;
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}
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return 0;
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overflow:
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pr_err("module %s: overflow in relocation type %d val %Lx\n",
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me->name, (int)ELF64_R_TYPE(rel[i].r_info), val);
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return -ENOEXEC;
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}
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int module_finalize(const Elf_Ehdr *hdr,
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const Elf_Shdr *sechdrs,
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struct module *me)
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{
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const Elf_Shdr *s, *se;
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|
const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
|
|
|
|
for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) {
|
|
if (strcmp(".altinstructions", secstrs + s->sh_name) == 0)
|
|
apply_alternatives_module((void *)s->sh_addr, s->sh_size);
|
|
#ifdef CONFIG_ARM64_MODULE_PLTS
|
|
if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) &&
|
|
!strcmp(".text.ftrace_trampoline", secstrs + s->sh_name))
|
|
me->arch.ftrace_trampoline = (void *)s->sh_addr;
|
|
#endif
|
|
}
|
|
|
|
return 0;
|
|
}
|