Stefan Agner 22039d150f clk: imx7d: create clocks behind rawnand clock gate ... The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Han Xu <han.xu@nxp.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2017-06-19 19:02:41 -07:00
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clk-busy.c	clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h	2016-01-29 12:59:50 -08:00
clk-cpu.c
clk-fixup-div.c	clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h	2016-01-29 12:59:50 -08:00
clk-fixup-mux.c	clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h	2016-01-29 12:59:50 -08:00
clk-gate2.c	clk: imx: clk-gate2: allow custom gate configuration	2016-03-31 17:01:55 +08:00
clk-gate-exclusive.c	clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h	2016-01-29 12:59:50 -08:00
clk-imx1.c	ARM: i.MX: Remove i.MX1 non-DT support	2016-08-09 22:47:26 +08:00
clk-imx6q.c	clk: imx6: don't restrict LDB mux changes on QuadPlus	2017-01-20 15:22:37 -08:00
clk-imx6sl.c	clk: imx: fix pll clock parents	2016-06-12 21:21:41 +08:00
clk-imx6sx.c	clk: imx: fix pll clock parents	2016-06-12 21:21:41 +08:00
clk-imx6ul.c	clk: imx: correct uart4_serial clock name in driver for i.MX6UL	2017-04-12 18:51:36 +02:00
clk-imx7d.c	clk: imx7d: create clocks behind rawnand clock gate	2017-06-19 19:02:41 -07:00
clk-imx21.c
clk-imx25.c
clk-imx27.c
clk-imx31.c	ARM: clk: imx31: properly init clocks for machines with DT	2016-11-01 16:44:46 +08:00
clk-imx35.c	ARM: clk-imx35: annotate clk enum with number values	2016-09-14 11:28:04 -07:00
clk-imx51-imx53.c	clk: imx53: Add clocks configuration	2016-09-20 16:52:06 -07:00
clk-pfd.c
clk-pllv1.c
clk-pllv2.c
clk-pllv3.c	clk: imx7d: Fix the DDR PLL enable bit	2017-06-06 17:42:41 -07:00
clk-vf610.c	clk: imx: pllv3: support fractional multiplier on vf610 PLL1/PLL2	2017-01-09 16:06:41 -08:00
clk.c
clk.h	clk: imx7d: Fix the powerdown bit location of PLL DDR	2017-06-01 00:25:38 -07:00
Makefile