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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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35e2916f70
Commit 4631960d26da ("ARM: imx6: set initial power mode in pm function")
moves imx6_set_lpm() from clock init function into
imx6_pm_common_init(). This causes a hang when cpuidle support is
enabled. The reason for that is ARM core clock is shut down
unexpectedly by WAIT mode. It happens with the following call stack:
cpuidle_register_governor()
cpuidle_switch_governor()
cpuidle_uninstall_idle_handler()
synchronize_sched()
wait_rcu_gp()
wait_for_completion()
When wait_for_completion() is called as above, all cores are idle/WFI.
Hence, the reset value of CCM_CLPCR_LPM - WAIT mode, will trigger a
hardware shutdown of the ARM core clock.
To fix the regression, we need to ensure that CCM_CLPCR_LPM is
initialized into RUN mode earlier than cpuidle governor registration,
which is a postcore_initcall. This patch creates function
imx6_pm_ccm_init() to map CCM block and initialize CCM_CLPCR_LPM into
RUN mode, and have the function called from machine .init_irq hook,
which should be early enough.
Reported-by: Kevin Hilman <khilman@kernel.org>
Fixes: 8fb76a07e2 ("ARM: imx6: set initial power mode in pm function")
Tested-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Tyler Baker <tyler.baker@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
111 lines
2.5 KiB
C
111 lines
2.5 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/irqchip.h>
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#include <linux/of_platform.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#include "cpuidle.h"
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static int ar8031_phy_fixup(struct phy_device *dev)
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{
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u16 val;
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/* Set RGMII IO voltage to 1.8V */
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phy_write(dev, 0x1d, 0x1f);
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phy_write(dev, 0x1e, 0x8);
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/* introduce tx clock delay */
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phy_write(dev, 0x1d, 0x5);
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val = phy_read(dev, 0x1e);
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val |= 0x0100;
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phy_write(dev, 0x1e, val);
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return 0;
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}
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#define PHY_ID_AR8031 0x004dd074
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static void __init imx6sx_enet_phy_init(void)
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{
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if (IS_BUILTIN(CONFIG_PHYLIB))
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phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
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ar8031_phy_fixup);
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}
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static void __init imx6sx_enet_clk_sel(void)
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{
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struct regmap *gpr;
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gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
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if (!IS_ERR(gpr)) {
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regmap_update_bits(gpr, IOMUXC_GPR1,
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IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);
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regmap_update_bits(gpr, IOMUXC_GPR1,
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IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);
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} else {
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pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
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}
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}
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static inline void imx6sx_enet_init(void)
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{
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imx6sx_enet_phy_init();
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imx6sx_enet_clk_sel();
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}
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static void __init imx6sx_init_machine(void)
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{
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struct device *parent;
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parent = imx_soc_device_init();
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if (parent == NULL)
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pr_warn("failed to initialize soc device\n");
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of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
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imx6sx_enet_init();
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imx_anatop_init();
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imx6sx_pm_init();
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}
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static void __init imx6sx_init_irq(void)
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{
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imx_gpc_check_dt();
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imx_init_revision_from_anatop();
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imx_init_l2cache();
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imx_src_init();
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irqchip_init();
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imx6_pm_ccm_init("fsl,imx6sx-ccm");
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}
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static void __init imx6sx_init_late(void)
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{
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imx6sx_cpuidle_init();
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if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
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platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
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}
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static const char * const imx6sx_dt_compat[] __initconst = {
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"fsl,imx6sx",
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NULL,
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};
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DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
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.init_irq = imx6sx_init_irq,
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.init_machine = imx6sx_init_machine,
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.dt_compat = imx6sx_dt_compat,
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.init_late = imx6sx_init_late,
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MACHINE_END
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