mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-01 17:26:39 +07:00
b3a1bde4db
The current implementation only assumes one GIC to be present in the system. However, there are platforms with more than one cascaded interrupt controllers (RealView/EB MPCore for example). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
43 lines
1.2 KiB
C
43 lines
1.2 KiB
C
/*
|
|
* linux/include/asm-arm/hardware/gic.h
|
|
*
|
|
* Copyright (C) 2002 ARM Limited, All Rights Reserved.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
#ifndef __ASM_ARM_HARDWARE_GIC_H
|
|
#define __ASM_ARM_HARDWARE_GIC_H
|
|
|
|
#include <linux/compiler.h>
|
|
|
|
#define GIC_CPU_CTRL 0x00
|
|
#define GIC_CPU_PRIMASK 0x04
|
|
#define GIC_CPU_BINPOINT 0x08
|
|
#define GIC_CPU_INTACK 0x0c
|
|
#define GIC_CPU_EOI 0x10
|
|
#define GIC_CPU_RUNNINGPRI 0x14
|
|
#define GIC_CPU_HIGHPRI 0x18
|
|
|
|
#define GIC_DIST_CTRL 0x000
|
|
#define GIC_DIST_CTR 0x004
|
|
#define GIC_DIST_ENABLE_SET 0x100
|
|
#define GIC_DIST_ENABLE_CLEAR 0x180
|
|
#define GIC_DIST_PENDING_SET 0x200
|
|
#define GIC_DIST_PENDING_CLEAR 0x280
|
|
#define GIC_DIST_ACTIVE_BIT 0x300
|
|
#define GIC_DIST_PRI 0x400
|
|
#define GIC_DIST_TARGET 0x800
|
|
#define GIC_DIST_CONFIG 0xc00
|
|
#define GIC_DIST_SOFTINT 0xf00
|
|
|
|
#ifndef __ASSEMBLY__
|
|
void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start);
|
|
void gic_cpu_init(unsigned int gic_nr, void __iomem *base);
|
|
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
|
|
void gic_raise_softirq(cpumask_t cpumask, unsigned int irq);
|
|
#endif
|
|
|
|
#endif
|