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84da009f06
Since insn.prefixes.nbytes can be bigger than the size of
insn.prefixes.bytes[] when a prefix is repeated, the proper
check must be:
insn.prefixes.bytes[i] != 0 and i < 4
instead of using insn.prefixes.nbytes. Use the new
for_each_insn_prefix() macro which does it correctly.
Debugged by Kees Cook <keescook@chromium.org>.
[ bp: Massage commit message. ]
Fixes: 25189d08e5
("x86/sev-es: Add support for handling IOIO exceptions")
Reported-by: syzbot+9b64b619f10f19d19a7c@syzkaller.appspotmail.com
Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/160697106089.3146288.2052422845039649176.stgit@devnote2
214 lines
4.6 KiB
C
214 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* AMD Encrypted Register State Support
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*
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* Author: Joerg Roedel <jroedel@suse.de>
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*/
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/*
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* misc.h needs to be first because it knows how to include the other kernel
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* headers in the pre-decompression code in a way that does not break
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* compilation.
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*/
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#include "misc.h"
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#include <asm/pgtable_types.h>
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#include <asm/sev-es.h>
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#include <asm/trapnr.h>
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#include <asm/trap_pf.h>
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#include <asm/msr-index.h>
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#include <asm/fpu/xcr.h>
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#include <asm/ptrace.h>
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#include <asm/svm.h>
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#include "error.h"
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struct ghcb boot_ghcb_page __aligned(PAGE_SIZE);
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struct ghcb *boot_ghcb;
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/*
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* Copy a version of this function here - insn-eval.c can't be used in
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* pre-decompression code.
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*/
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static bool insn_has_rep_prefix(struct insn *insn)
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{
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insn_byte_t p;
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int i;
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insn_get_prefixes(insn);
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for_each_insn_prefix(insn, i, p) {
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if (p == 0xf2 || p == 0xf3)
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return true;
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}
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return false;
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}
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/*
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* Only a dummy for insn_get_seg_base() - Early boot-code is 64bit only and
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* doesn't use segments.
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*/
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static unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx)
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{
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return 0UL;
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}
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static inline u64 sev_es_rd_ghcb_msr(void)
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{
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unsigned long low, high;
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asm volatile("rdmsr" : "=a" (low), "=d" (high) :
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"c" (MSR_AMD64_SEV_ES_GHCB));
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return ((high << 32) | low);
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}
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static inline void sev_es_wr_ghcb_msr(u64 val)
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{
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u32 low, high;
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low = val & 0xffffffffUL;
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high = val >> 32;
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asm volatile("wrmsr" : : "c" (MSR_AMD64_SEV_ES_GHCB),
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"a"(low), "d" (high) : "memory");
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}
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static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt)
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{
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char buffer[MAX_INSN_SIZE];
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enum es_result ret;
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memcpy(buffer, (unsigned char *)ctxt->regs->ip, MAX_INSN_SIZE);
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insn_init(&ctxt->insn, buffer, MAX_INSN_SIZE, 1);
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insn_get_length(&ctxt->insn);
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ret = ctxt->insn.immediate.got ? ES_OK : ES_DECODE_FAILED;
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return ret;
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}
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static enum es_result vc_write_mem(struct es_em_ctxt *ctxt,
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void *dst, char *buf, size_t size)
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{
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memcpy(dst, buf, size);
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return ES_OK;
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}
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static enum es_result vc_read_mem(struct es_em_ctxt *ctxt,
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void *src, char *buf, size_t size)
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{
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memcpy(buf, src, size);
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return ES_OK;
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}
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#undef __init
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#undef __pa
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#define __init
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#define __pa(x) ((unsigned long)(x))
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#define __BOOT_COMPRESSED
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/* Basic instruction decoding support needed */
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#include "../../lib/inat.c"
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#include "../../lib/insn.c"
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/* Include code for early handlers */
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#include "../../kernel/sev-es-shared.c"
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static bool early_setup_sev_es(void)
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{
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if (!sev_es_negotiate_protocol())
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sev_es_terminate(GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED);
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if (set_page_decrypted((unsigned long)&boot_ghcb_page))
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return false;
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/* Page is now mapped decrypted, clear it */
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memset(&boot_ghcb_page, 0, sizeof(boot_ghcb_page));
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boot_ghcb = &boot_ghcb_page;
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/* Initialize lookup tables for the instruction decoder */
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inat_init_tables();
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return true;
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}
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void sev_es_shutdown_ghcb(void)
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{
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if (!boot_ghcb)
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return;
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if (!sev_es_check_cpu_features())
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error("SEV-ES CPU Features missing.");
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/*
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* GHCB Page must be flushed from the cache and mapped encrypted again.
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* Otherwise the running kernel will see strange cache effects when
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* trying to use that page.
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*/
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if (set_page_encrypted((unsigned long)&boot_ghcb_page))
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error("Can't map GHCB page encrypted");
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/*
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* GHCB page is mapped encrypted again and flushed from the cache.
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* Mark it non-present now to catch bugs when #VC exceptions trigger
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* after this point.
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*/
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if (set_page_non_present((unsigned long)&boot_ghcb_page))
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error("Can't unmap GHCB page");
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}
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bool sev_es_check_ghcb_fault(unsigned long address)
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{
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/* Check whether the fault was on the GHCB page */
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return ((address & PAGE_MASK) == (unsigned long)&boot_ghcb_page);
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}
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void do_boot_stage2_vc(struct pt_regs *regs, unsigned long exit_code)
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{
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struct es_em_ctxt ctxt;
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enum es_result result;
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if (!boot_ghcb && !early_setup_sev_es())
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sev_es_terminate(GHCB_SEV_ES_REASON_GENERAL_REQUEST);
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vc_ghcb_invalidate(boot_ghcb);
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result = vc_init_em_ctxt(&ctxt, regs, exit_code);
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if (result != ES_OK)
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goto finish;
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switch (exit_code) {
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case SVM_EXIT_RDTSC:
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case SVM_EXIT_RDTSCP:
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result = vc_handle_rdtsc(boot_ghcb, &ctxt, exit_code);
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break;
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case SVM_EXIT_IOIO:
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result = vc_handle_ioio(boot_ghcb, &ctxt);
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break;
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case SVM_EXIT_CPUID:
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result = vc_handle_cpuid(boot_ghcb, &ctxt);
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break;
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default:
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result = ES_UNSUPPORTED;
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break;
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}
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finish:
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if (result == ES_OK) {
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vc_finish_insn(&ctxt);
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} else if (result != ES_RETRY) {
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/*
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* For now, just halt the machine. That makes debugging easier,
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* later we just call sev_es_terminate() here.
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*/
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while (true)
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asm volatile("hlt\n");
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}
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}
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